Vertical MOSFET with asymmetric gate structure

A semiconductor process, comprising:

• forming a semiconductor wall over an upper surface of a semiconductor substrate, wherein the wall is electrically isolated from the substrate;
• forming first and second gate dielectrics contacting first and second faces respectively of the semiconductor wall wherein dielectric constants of the first and second gate dielectrics differ;
• forming first and second gate electrodes contacting the first and second gate dielectrics respectively, wherein a doping of the first and second gate electrodes differs and wherein the first and second gate electrodes lie over a channel portion of the wall;
• and
• forming source/drain structures contacting portions of the wall not covered by the first and second gate electrodes.

A process of forming a transistor, comprising:

• forming a semiconductor channel structure having first and second major surfaces, the channel structure overlying and electrically isolated from a semiconductor substrate;
• forming first and second gate dielectrics on the first and second major surfaces respectively, wherein the first and second gate dielectric differ in at least one characteristic;
• and
• forming first and second gate electrodes in contact with the first and second gate dielectrics respectively, wherein the first and second gate electrodes differ in at least one characteristic;
• wherein forming the channel structure comprises forming a first structure having at least one sidewall, depositing a semiconductor film over the first structure, and crystallizing the deposited semiconductor film.