Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array

A method for producing a memory cell array, said method comprising the following steps:

• a) providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers;
• b) producing bit line recesses in said gate region layer, said bit line recesses extending down to the storage medium layer;
• c) producing insulating spacer layers on lateral surfaces of said bit line recesses;
• d) removing the sequence of storage medium layers fully or partly in the area of the bit line recesses;
• e) executing a source/drain implantation in the area of said bit line recesses;
• f) removing the sequence of storage medium layers completely in the area of the bit line recesses, if said sequence of storage medium layers was not removed completely in step d);
• g) producing metallizations on the areas subjected to the source/drain implantation, so as to produce metallic bit lines, said metallizationS being insulated from the gate region layer by the insulating spacer layers;
• h) filling the bit line recesses remaining after the production of the metallic bit lines with an insulating material;
• and
• i) producing word lines which extend substantially at right angles to said bit lines and which are each connected to a plurality of gate regions, said gate regions being produced when the word lines are being produced, by means of suitable patterning of the remaining parts of the gate region layer, wherein step i) comprises the following sub-steps:
• i1) full-area application of a polycrystalline layer;
• i2) patterning the polycrystalline layer and the remaining parts of the gate region layer in accordance with the pattern of the word lines, whereby the gate regions are produced;
• i3) filling the recesses produced in step i2) in the polycrystalline layer and in the gate region layer with an insulating material;
• and
• i4) executing a suicide process for selectively producing a silicide layer on the polycrystalline layer patterned with the word-line pattern, so as to produce metallic word lines.