Method of forming low-resistivity connections in non-volatile memories

A method comprising:

• forming, on a semiconductor substrate material, a plurality of memory cells arranged in a matrix having row lines and column lines, each having first, second, and third teminals, wherein the first terminals of the memory cells of a given row of the matrix comprise a first conductive region, the second terminals of the memory cells of a given row comprise a second conductive region, and the third terminals of adjacent pairs of the memory cells of a given column comprise a plurality of conductive regions;
• forming a first layer of dielectric material on the semiconductor substrate material and covering the memory cells;
• forming a first channel in the first layer of dielectric material, which is delimited by the first conductive region and extends a substantial portion of the length thereof;
• forming a second channel in the first layer of dielectric material, which is delimited by the second conductive region and extends a substantial portion of the length thereof;
• forming a plurality of holes in the first layer of dielectric material, each of which is delimited by one of the plurality of conductive regions;
• forming a layer of conductive material, having a lower resistivity than that of the first, second, or plurality of conductive regions, such that it fills the first channel, the second channel, and the plurality of holes, and making electrical contact thereby with the respective conductive regions;
• leveling the surface of the conductive material and the layer of dielectric material, such that the conductive material is eliminated from the surface of the dielectric material, and remains only in the first channel, the second channel, and the plurality of holes, thereby electrically isolating the respective channels and plurality of holes;
• forming a strip of conductive material above, and in electrical contact with the plurality of conductive traces;
• forming a second layer of dielectric material on the upper surface of the first layer of dielectric material and covering the strip of conductive material;
• forming a first additional hole in the second layer of dielectric material directly above the first channel, a second additional hole in the second layer of dielectric material directly above the second channel, and a third additional hole in the second layer of dielectric material directly above the strip of conductive material;
• forming a first conductive trace, within and substantially filling the first additional hole, and in electrical contact with the conductive material in the first channel;
• forming a second conductive trace, within and substantially filling the second additional hole, and in electrical contact with the conductive material in the second channel;
• forming a third conductive trace, within and substantially filling the third additional hole, and in electrical contact with the strip of conductive material.

A method of forming connections in a device having a plurality of memory cells, comprising:

• forming a dielectric layer on a first plurality, a second plurality and a third plurality of conductive lines wherein each conductive line of the first, second and third pluralities has a first resistivity;
• selectively removing a portion of the dielectric layer on each of the first, second and third pluralities of conductive lines to an extent of exposing a surface of each of the first, second and third pluralities of conductive lines, and the portion extends a substantial distance of each of the conductive lines of the first, second, and third pluralities;
• and
• forming a conductive strip on each of the surfaces of the conductive lines on each of the first, second and third pluralities of conductive lines wherein the conductive line has a second resistivity and simultaneously electrically couples the plurality of memory cells.

A method of forming conductive lines in a memory device having memory cells formed in a matrix in a semiconductor substrate comprising:

• forming a plurality of conductive regions having a surface and a first resistivity;
• forming a dielectric layer on the plurality of conductive regions;
• selectively removing the dielectric layer to form a removed portion of the dielectric layer to an extent such that the surface of each conductive region of the plurality of conductive regions is exposed, and such that the removed portion extends for a plurality of memory cells and is coincident with a substantial length of the conductive regions of the plurality of conductive regions;
• and
• forming a line within each removed portion of the dielectric layer of each of the conductive regions such that the line electrically contacts the surface of the conductive region, and the line having a second resistivity being less than the first resistivity of the conductive region.