Mask-alignment detection circuit in x and y directions

A mask-alignment detection circuit formed on a semiconductor wafer, the wafer having a surface defining a plane having X and Y dimensions, the detection circuit comprising:

• a. a diffusion region formed in the surface of the wafer and patterned to occupy a diffusion area parallel to the plane;
• b. first and second test terminal connected to the first diffusion region;
• c. an insulating layer formed on the surface of the semiconductor wafer and patterned to include a window over at least a portion of the first diffusion area between the first and second terminals, wherein the window and the diffusion area overlap one another to form an overlap area;
• d. wherein the overlap area is proportional to a first extent to which the diffusion region and the window are aligned in the X dimension and is independent of a second extent to which the diffusion region and the window are aligned in the Y dimension;
• and
• e. wherein the diffusion region and the window are aligned in the X dimension to within a first maximum alignment tolerance and in the Y dimension to a second maximum alignment tolerance.

A circuit for measuring an extent of misalignment between integrated-circuit features and a plurality of simultaneously formed diffusion regions, the circuit comprising:

• a. a first one of the plurality of diffusion regions having a first width and a first length and including first and second test terminals;
• b. a second one of the plurality of diffusion regions having a second width and a second length and including third and fourth test terminals;
• c. wherein the first width varies in proportion to the extent of misalignment and the second width varies in inverse proportion to the extent of misalignment;
• d. means for measuring a first resistance between the first and second test terminals and for measuring a second resistance between the third and fourth test terminals.