Delay lock loop circuit useful in a synchronous system and associated methods

A method of locking a delay lock loop in synchronization with a clock signal, comprising:

• initializing a variable delay circuit within the delay lock loop to a minimum delay value, wherein the output of the variable delay circuit is coupled to a feedback loop, and wherein delay of the variable delay circuit is controlled by a control signal generated by a feedback loop;
• frequency dividing the clock signal and inputting it into the variable delay circuit;
• locking the frequency-divided clock signal by adjusting the control signal to the variable delay circuit;
• and
• undividing the frequency-divided clock signal.

A delay lock loop circuit, comprising:

• a variable delay circuit configured to receive either a clock signal or a frequency divided version of the clock signal;
• a phase detector for receiving as inputs (i) either the output of the variable delay circuit or a frequency divided version of the output of the variable delay circuit, and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs;
• and
• a feedback loop for receiving the first signal and for producing a control signal;
• wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.

A memory device accessible by a first clock signal, comprising:

• a memory array accessible by a second clock signal;
• and
• a delay lock loop for synchronizing the second clock signal with the first clock signal, comprising:
• a variable delay circuit for producing the second clock signal, wherein the variable delay circuit is configured to receive either the first clock signal or a frequency divided version of the first clock signal;
• a phase detector for receiving as inputs (i) either the second clock signal or a frequency divided version of the second clock signal, and (ii) the frequency divided version of the first clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs;
• and
• a feedback loop for receiving the first signal and for producing a control signal;
• wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.

A system, comprising:

• a microprocessor for producing a first clock signal;
• a memory device for receiving the first clock signal, the memory device comprising a memory array accessible by a second clock signal;
• and
• a delay lock loop for synchronizing the second clock signal with the first clock signal, comprising:
• a variable delay circuit for producing the second clock signal, wherein the variable delay circuit is configured to receive either the first clock signal or a frequency divided version of the first clock signal;
• a phase detector for receiving as inputs (i) either the second clock signal or a frequency divided version of the second clock signal, and (ii) the frequency divided version of the first clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs;
• and
• a feedback loop for receiving the first signal and for producing a control signal;
• wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.