MPEG decoder using a shared memory
AssigneeSTMicrolectronics S.A.
InventorsJean-Michel Moutin, Pierre Marty
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Abstract
A circuit includes a microprocessor, an MPEG decoder for decoding an image sequence, and a memory common to the microprocessor and to the decoder. The circuit also includes a circuit for evaluating a decoder delay, a control circuit for, if the decoder delay is greater than a predetermined level, granting the decoder a memory access priority, and otherwise, granting the microprocessor the memory access priority.
Claims23
A circuit including a microprocessor, an MPEG decoder for decoding an image sequence, and a memory common to the microprocessor and to the decoder, comprising:
- an evaluation circuit for evaluating a decoder delay of the MPEG decoder;
- and,
- a control circuit for, if the decoder delay is greater than a predetermined level, granting the decoder a memory access priority, and otherwise, granting the microprocessor the memory access priority.
A method of sharing a common memory between a microprocessor and an image decoder for decoding an image sequence, the method comprising:
- communicatively linking the memory to a control circuit, the control circuit controlling access to the memory;
- communicatively linking the image decoder to the control circuit;
- communicatively linking the microprocessor to the control circuit;
- evaluating an image decoder delay of the image decoder;
- and
- providing a control signal to the control circuit, the control signal configured to instruct the control circuit to grant the image decoder a memory access priority only when the image decoder delay is greater than a predetermined level, and otherwise grant the microprocessor the memory access priority.
A circuit for evaluating a delay of an image decoder comprising:
- an activity determination circuit that determines whether the image decoder is unused during a clock cycle;
- a counter that is coupled to the activity determination circuit and structured to update a count value when the image decoder is unused during a clock cycle;
- an arithmetic logic unit that adjusts the count value with an activity threshold value once a reference period;
- and
- a comparator for determining a sign of the count value.
A method of sharing a common memory between a microprocessor and an image decoder for decoding an image sequence, the method comprising:
- determining an image decoder delay based on an activity level of the image decoder;
- granting the image decoder a memory access priority only when the image decoder delay is greater than a predetermined level, thereby temporarily debasing microprocessor performance;
- and
- otherwise granting the microprocessor the memory access priority.
Dependencies are inferred from the claim text.