Dynamic floating SCR (semiconductor-controlled-rectifier) ESD protection
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTa-Lee Yu, Jian-Hsing Lee
Life of this patent
Estimating the term…
Abstract
This invention provides a circuit and a method for protecting electronic circuits from electrostatic damage ESD. The invention teaches a dynamic floating silicon-controlled rectifier SCR for use as an ESD clamp. The n-well of the SCR is biased to the supply voltage Vdd under normal conditions to provide good latch-up performance. During ESD events, the n-well is floated to improve clamping performance. In addition, this invention utilizes a floating-well control circuit which provides better latch-up immunity during normal operation after the ESD event has passed.
Claims27
A circuit to protect other circuits from Electrostatic Discharge (ESD) damage comprising:
- A floating-well circuit connected between a supply voltage Vdd and an N-well of a silicon-controlled rectifier, (SCR),
- an N+ region imbedded in said N-well and
- a connection to said N-well via a connection to said N+ region.
A floating-well circuit comprising:
- a capacitor whose one node connected to said supply voltage Vdd and another node connected to one-side of a resistor, and to the gate of a PMOS field effect transistor,
- said resistor which is connected to said capacitor and to ground,
- a PMOS field effect transistor (FET) whose gate is attached to said capacitor whose drain is connected to said supply voltage VCC and whose drain is connected to the N-well of the PNPN SCR.
A floating-well circuit comprising:
- a capacitor whose one node connected to said supply voltage Vdd and another node connected to the drain of an NMOS FET, and to the gate of a PMOS field effect transistor,
- said NMOS FET whose source is connected to ground and its gate is connected to a second capacitor whose other node is connected to ground,
- said NMOS FET whose gate is also connected to a resistor whose other node is connected to the supply voltage Vdd,
- said PMOS field effect transistor (FET) whose drain is connected to said supply voltage Vdd and whose source is connected to the N-well of the PNPN SCR.
A floating-well circuit comprising:
- a capacitor whose one node connected to said supply voltage Vdd and another node connected to the drain of an NMOS FET, and to the gate of a PMOS field effect transistor,
- said NMOS FET whose source is connected to ground and its gate is connected to the supply voltage Vdd and,
- said PMOS field effect transistor (FET) whose drain is connected to said supply voltage Vdd and whose source is connected to the N-well of the PNPN SCR.
A method of protecting circuits from electrostatic discharge ESD damage comprising the steps of:
- connecting a floating-well circuit between the power supply voltage Vdd and the N-well of an SCR;
- imbedding an N+ region in said N-well, and
- connecting to said N-well via a connection to said N+ region.
A simulation model of an ESD protection circuit comprising:
- a simulation model of a PNPN SCR, a floating well circuit inserted between the power supply voltage Vdd and the N-well of an SCR wherein said floating well circuit comprises a capacitor whose one node connected to a supplv voltage Vdd and another node connected to one side of a resistor, and to a sate of a PMOS field effect transistor said resistor which is connected to said capacitor and to around, and a PMOS field effect transistor (FET) whose gate is attached to said capacitor whose drain is connected to a supply voltage VCC and whose drain is connected to the N-well of said PNPN SCR.
Dependencies are inferred from the claim text.