Barrier metal oxide interconnect cap in integrated circuits
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Pin-Chin Connie Wang
Life of this patent
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Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. An interconnect cap is disposed over the conductor core and seed layer and is capped with a capping layer. The interconnect cap is preferably of an indium oxide compound.
Claims8
An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
- a dielectric layer formed on the semiconductor substrate having an opening provided therein;
- a conductor core filling the opening and connected to the semiconductor device;
- a barrier metal oxide interconnect cap disposed over the conductor or and recessed in the opening in the dielectric layer;
- and
- capping layer disposed over the barrier metal oxide interconnect cap.
An integrated circuit comprising:
- silicon substrate having a semiconductor device provided thereon;
- a device oxide layer formed on the silicon substrate;
- a channel oxide layer formed on the device oxide layer having a channel opening provided therein;
- a barrier layer lining the channel opening;
- a seed layer lining the barrier layer;
- a conductor core filling the channel opening and connected to the semiconductor device, the conductor core over the seed layer;
- a barrier metal oxide interconnect cap disposed over the conductor core and the seed layer and recessed in the channel opening in the channel oxide layer;
- and
- a capping layer disposed over the barrier metal oxide and the dielectric layer.
Dependencies are inferred from the claim text.