Memory cell and production method
AssigneeInfineon Technologies AG
InventorJosef Willer
Life of this patent
Estimating the term…
Abstract
A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate electrode is a component of a strip-shaped word line. Source and drain regions are disposed between gate electrodes of adjacent memory cells. Source regions are provided with polysilicon layers, in the form of a strip, as common source lines. Drain regions are connected as bit lines through polysilicon fillings to metallic interconnects applied to the top face of the semiconductor body.
Claims14
A memory cell disposed on a semiconductor body having a top face, the memory cell comprising:
- a source region formed at the top face;
- a drain region;
- a gate line;
- a gate electrode disposed between said source region and said drain region at said top face, said gate electrode being part of said gate line, said gate line structured in strips and being a word line;
- a source line being a common source connection for a plurality of memory cells, said source line electrically contacting said source region between said gate electrode and another gate electrode of another of the plurality of memory cells;
- a drain line being a metallic interconnect electrically conductively connected to said drain region and disposed as a bit line running transversely with respect to said gate line and electrically isolated from said gate line;
- supply leads respectively connected to said source line, said drain line, and said gate line;
- and
- a memory layer structure having:
- a first boundary layer;
- a second boundary layer;
- and
- a memory layer disposed in between said first boundary layer and said second boundary layer;
- said memory layer serving as an actual storage medium;
- said memory layer, said first boundary layer, and said second boundary layer each made from a material having a repective energy band gap;
- said material of said memory layer having a relatively narrow energy band gap;
- said material of said first boundary layer and said second boundary layer having a relatively wide energy band gap;
- and
- said memory layer structure disposed between said semiconductor body and said gate electrode;
- and
- said source line running transversely with respect to said bit line.
Dependencies are inferred from the claim text.