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US 6,674,105 B2Granted
Semiconductor memory device and method of forming the same
AssigneeNEC Corporation
InventorKiyotaka Iwai
Life of this patent
Estimating the term…
Abstract
In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the n-channel MOS field effect transistors forming the flip flop. Namely, the p-channel MOS field effect transistors serving as the driver gates have a larger gate length and a smaller gate oxide film thickness than the n-channel MOS field effect transistors forming the flip flop.
Claims2
A static random access memory including:
- a first n-channel MOS field effect transistor being connected in series between a first node and a ground line and said first n-channel MOS field effect transistor having a gate connected to a second node, and said first node having a voltage supplied by only said ground line or a first bit line;
- a second n-channel MOS field effect transistor being connected in series between a second node and the ground line and said second n-channel MOS field effect transistor having a gate connected to the first node, and said second node having a voltage supplied by only said ground line or a second bit line;
- a first p-channel MOS field effect being connected in series between the first node and said first bit line and said first p-channel MOS field effect transistor having a gate connected to a word line;
- and
- a second p-channel MOS field effect being connected in series between the second node and said second bit line adjacent to said first bit line and said second p-channel MOS field effect transistor having a gate connected to said word line,
- wherein said first and second n-channel MOS field effect transistors have gate insulation films that are thicker than gate insulation films of said first and second p-channel MOS field effect transistors to suppress a leakage of gate tunneling current and
- wherein said gates of said first and second n-channel MOS field effect transistors are doped with an n-type impurity and said gates of said first and second p-channel MOS field effect transistors are doped with an p-type impurity.
4 more elements
Dependencies are inferred from the claim text.