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US 6,673,720 B2Granted
Method for improving the reliability of flash memories
AssigneeMacronix International Co., Ltd.
InventorsWeng-Hsing Huang, Kent Kuohua Chang
Life of this patent
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Abstract
A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.
Claims7
A method for improving the reliability of flash memories, the method comprising:
- forming a stacked layer on a substrate, wherein the stacked layer comprises a polysilicon layer and a sacrificial layer formed atop the polysilicon layer;
- forming a HTO (high temperature oxide) film to cover the surface of the stacked layer and the substrate;
- depositing a dielectric layer on the HTO film;
- partially removing the dielectric layer and the HTO film to expose parts of the sacrificial layer while a part of the HTO film remains adjacent to the sidewall of the polysilicon layer;
- and
- completely removing the sacrificial layer;
- wherein the HTO film adjacent to the sidewall of the polysilicon layer reinforces the interface between the dielectric layer and the polysilicon layer to prevent acid-corroded seams being formed.
4 more elements
Dependencies are inferred from the claim text.