Method of manufacturing a MISFET having post oxide films having at least two kinds of thickness

A method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of:

• providing gate insulating films of said first and second MISFETs on a semiconductor substrate;
• providing gate electrodes on said gate insulating films;
• implanting ions selected from the group consisting of ions that permit changing the oxidizing rate, ions that permit changing the nitriding rate and ions that permit changing the oxynitriding rate into regions in which said first MISFET is to be formed;
• covering the gate electrodes of said first and second MISFETs with an insulating material film, said insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said first and second MISFETs;
• and
• forming, after the gate electrodes of said first and second MISFETs are covered with said insulating material film, a source region and a drain region in the surface region of said semiconductor substrate by ion implantation through said first region of said covering insulating film with the gate electrode used as a mask in said first and second MISFETs;
• wherein, in the case of implanting ions that permit changing the oxidizing rate, said covering insulating film is a semiconductor oxide film;
• in the case of implanting ions that permit changing the nitriding rate, said covering insulating film is a semiconductor nitride film;
• and in the case of implanting ions that permit changing the oxynitriding rate, said covering insulating film is a semiconductor oxynitride film.

A method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of:

• providing gate insulating films of said first and second MISFETs on a semiconductor substrate;
• providing an electrode material film providing the basis of a gate electrode on said gate insulating films;
• etching said electrode material film in said first MISFET so as to form said gate electrode;
• covering, after said etching step, the gate electrode in said first MISFET and said electrode material film in said second MISFET with a first insulating material film, said first insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said first MISFET;
• etching said first insulating film and said electrode material film in said second MISFET so as to form said gate electrode;
• removing the first insulating material film in said second MISFET after said etching step;
• covering the gate electrode with a second insulating material film in said second MISFET after removal of said first insulating material film, said second insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and second region arranged on the side surfaces of the gate electrode and the gate insulating film in said second MISFET;
• and
• forming, after the gate electrode of said second MISFET is covered with said second insulating material film, a source region and a drain region in the surface region of said semiconductor substrate by ion implantation through said first region of said covering insulating film with the gate electrode used as a mask in said first and second MISFETs.