US 6,673,695 B1Granted

STI scheme to prevent fox recess during pre-CMP HF dip

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsVictor Seng-Keong Lim, Paul Proctor

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Abstract

A new method is provided for the creation of STI regions. STI trenches are created in the surface of a substrate following conventional processing. A layer of STI oxide is deposited and, using an exposure mask that is a reverse mask of the mask that is used to create the STI pattern, impurity implants are performed into the surface of the deposited layer of STI oxide. In view of these processing conditions, the layer of STI oxide overlying the patterned layer of etch stop material is exposed to the impurity implants. This exposure alters the etch characteristics of the deposited layer of STI oxide where this STI oxide overlies the patterned layer of etch stop material. The etch rate of the impurity exposed STI oxide is increased by the impurity implantation, resulting in an etch overlying the patterned etch stop layer that proceeds considerably faster than the etch of the STI oxide that is deposited overlying the created STI trenches. With the significantly faster etch of the STI oxide where this oxide has been exposed to impurity implantation, the STI oxide removal can be equalized between the STI oxide that overlies the patterned etch stop layer and the oxide that has been deposited over the STI trenches.

Claims44

Dependent claims

A method of creating regions of Shallow Trench Isolation (STI) in the surface of a substrate, comprising the steps of:

providing a substrate, the substrate is provided with an objective of creating semiconductor devices over the surface thereof;
creating a layer of pad oxide over the surface of said substrate;
depositing a layer of etch stop material over the surface of said layer of pad oxide;
patterning and etching said layer of etch stop material and said layer of pad oxide using a first exposure mask, creating at least one opening through said layers of etch stop material and said layer of pad oxide, said at least one opening being aligned with at least one surface area over the surface of said substrate where at least one region of Shallow Trench Isolation is to be created;
creating at least one STI trench in the surface of said substrate in accordance with said at least one opening created through said layers of etch stop material and said layer of pad oxide;
blanket depositing a layer of STI dielectric over the surface of said patterned and etched layer of etch stop material, filling said at least one opening created through said layers of etch stop material and said layer of pad oxide, further filling said at least one STI trench created in the surface of said substrate;
creating an impurity ion implantation blocking mask over the surface of said layer of STI dielectric using a second exposure mask, said second exposure mask being a reverse mask of said first exposure mask, blocking the surface of said layer of STI dielectric where said layer of STI dielectric overlies said at least one STI trench created in the surface of said substrate;
performing an impurity ion implantation into the exposed surface of said layer of STI dielectric in accordance with said ion implantation blocking mask, creating at least two first layers of doped STI dielectric overlying said patterned and etched layer of etch stop material, said at least two first layers of doped STI dielectric surrounding at least one second layer of undoped STI dielectric overlying said at least one STI trench created in the surface of said substrate, increasing an etch rate of said at least two first layers of doped STI dielectric by a measurable amount;
removing said impurity ion implantation blocking mask from the surface of said layer of STI dielectric;
etching said at least two first doped and said at least one second undoped layers of STI dielectric to where said layer of STI dielectric overlies the surface of said patterned and etched layer of etch stop material to a measurable height;
and
removing said layer of STI dielectric from the surface of said patterned and etched layer of etch stop material.

9 more elements

A method of creating regions of Shallow Trench Isolation (STI) in the surface of a substrate, comprising the steps of:

providing a substrate, the substrate is provided with an objective of creating semiconductor devices over the surface thereof;
creating at least one STI trench in the surface of said substrate using a first exposure mask;
depositing a layer of STI dielectric over the surface of said substrate, filling said at least one STI trench created in the surface of said substrate;
selectively modifying an etch rate of at least two first cross sections of said deposited layer of STI dielectric, said at least two first cross sections being adjacent to said at least one STI trench created in the surface of said substrate;
and
removing said layer of STI dielectric from above the surface of said substrate, leaving said STI dielectric deposited inside said at least one trench created in the surface of said substrate.

3 more elements

A method of creating regions of Shallow Trench Isolation (STI) in the surface of a substrate, comprising the steps of:

providing a substrate, the substrate is provided with an objective of creating semiconductor devices over the surface thereof;
creating a layer of pad oxide over the surface of said substrate;
depositing a layer of etch stop material over the surface of said layer of pad oxide;
patterning and etching said layer of etch stop material and said layer of pad oxide using a first exposure mask, creating at least one opening through said layers of etch stop material and said layer of pad oxide, said at least one opening being aligned with at least one surface area over the surface of said substrate where at least one region of Shallow Trench Isolation is to be created;
creating at least one STI trench in the surface of said substrate in accordance with said at least one opening created through said layers of etch stop material and said layer of pad oxide;
blanket depositing a layer of STI dielectric over the surface of said patterned and etched layer of etch stop material, filling said at least one opening created through said layers of etch stop material and said layer of pad oxide, further filling said at least one STI trench created in the surface of said substrate;
creating an impurity ion implantation blocking mask over the surface of said layer of STI dielectric using a second exposure mask, said second exposure mask being a reverse mask of said first exposure mask, blocking the surface of said layer of STI dielectric where said layer of STI dielectric overlies said at least one STI trench created in the surface of said substrate;
etching said layer of STI dielectric to where said layer of STI dielectric overlies the surface of said patterned and etched layer of etch stop material to a measurable height;
performing an impurity ion implantation into the exposed surface of said layer of STI dielectric in accordance with said ion implantation blocking mask;
removing said impurity ion implantation blocking mask from the surface of said layer of STI dielectric;
and
removing said layer of STI dielectric from the surface of said patterned and etched layer of etch stop material.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/062,657Filed 1 Feb 2002
Granted: 6 Jan 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/0143
Using trench refilling with dielectric materials, e.g. shallow trench isolations: comprising concurrently refilling multiple trenches having…
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by