Method for manufacturing a multi-bit memory cell

A method for manufacturing a memory cell circuit, which comprises the steps of:

• providing a body selected from the group consisting of a semiconductor body and a layer of semiconductor material forming the body;
• providing a series of layers on the body, the series of layers including a first oxide layer, a memory layer above the first oxide layer and intended for storing charge carriers, and a second oxide layer above the memory layer;
• removing the memory layer outside a region intended for a memory cell;
• carrying out an implantation of a doping material in the body for forming a source region and a drain region separated by a channel region and disposed below the series of layers;
• providing an auxiliary layer outside the region occupied by the memory layer, the auxiliary layer having a recess in the region of the memory layer with sufficiently steep edges;
• forming spacers in the recess at the edges of the auxiliary layer;
• removing part of the memory layer disposed between the spacers;
• forming a dielectric layer between the spacers;
• forming a gate electrode on the dielectric layer and structuring the dielectric layer and the gate electrode;
• and
• applying a conductor track, the conductor track being electrically conductively connected to the gate electrode.