US 6,673,657 B2Granted

Kill index analysis for automatic defect classification in semiconductor wafers

AssigneeApplied Materials, Inc.

InventorsAyelet Pnueli, Ariel Ben-Porath

Life of this patent

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Abstract

A kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. The method relates to an analysis of the geometrical relationship between non-predetermined portion(s), generally referred to as defects, and the surrounding predetermined topology of a conductive semiconductor pattern, to determine the effect of defects on the functionality and reliability of a wafer, and particularly an examined die thereon. Further, in accordance with this geometrical information, a preferred classification of the effects of defects into a numerical value, the “kill index”, is achieved. Preferably, this kill index is strongly linked, correlated and related to the damage caused by the defect to the functionality and/or reliability of the underlying integrated circuit.

Claims5

Dependent claims

A computer program product including a computer usable medium having computer readable program code embodied therein for a kill index classification method for prioritizing relational aspects of topological defect intersections in a semiconductor fabrication process, the computer readable program code in said computer usable medium including at least one program code selected from:

a) first computer readable program code for causing a computer to locate a region having at least one non-predetermined portion therein;
b) tied to the first computer readable program code, second computer readable program code for causing the computer to determine a predetermined topology for the region;
c) tied to the second computer readable program code, third computer readable program code for causing the computer to calculate evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region;
and
d) tied to the third computer readable program code, fourth computer readable program code for causing the computer to assign a kill index classification using the calculated evaluation parameters;
wherein the kill index classification method includes the steps of
a) locating a region having at least one non-predetermined portion therein;
b) determining a predetermined topology for the region;
c) calculating evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region;
and
d) assigning a kill index classification using the calculated evaluation parameters.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/195,769Filed 11 Jul 2002 · division
Priority: 30 Mar 2001
Published: US 2003/0017664 A123 Jan 2003
Granted: 6 Jan 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification2 codes

H10P 74/23
Testing or measuring during manufacture or treatment of wafers, substrates or devices: characterised by multiple measurements, corrections,…
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered

Family

Application09/822,919Parent of this division · filed 30 Mar 2001
US 2003/0017664 A1Pre-grant publication · published 23 Jan 2003
US 2002/0142522 A1Published application
US 6,605,478 B2Related patent
US 6,673,657 B2This patent

From the US filing history. Foreign family members aren’t listed.