US 6,665,857 B2 · System and method of generating integrated circuit mask data

Abstract

Masks from which integrated circuits are manufactured are derived from layers found in integrated circuit designs. The mapping from design layers to mask layers produces masks with various essential properties. The operators that transform the design layers to the mask layers consist of the Boolean operations along with fattening and shrinking. This invention shortens the compute time used in carrying out these operations by keeping all temporary layers in main memory and never on disk, avoiding both disk space and access time as a result. Temporary layers are extra, intermediate layers used in computing the final mask layers. The savings are achieved by slicing the design into slightly overlapping pieces, each of which can fit in main memory, and carrying out the operations upon all layers of each piece before beginning the next piece.

Claims20

Dependent claims

A method of generating mask layer layout data for an integrated circuit, including the steps of:

(a) defining a rectangular region size, to be used to partition geometrically a given integrated circuit design into adjacent regions;
(b) defining a constant amount of overlap between the adjacent regions, which, along with said rectangular region size, defines a set of overlapping rectangular regions corresponding to the given integrated circuit design;
(c) reading layout layers in electronic form from an integrated-circuit design file and writing a set of polygons for each layer onto a storage device;
wherein one or more sets of polygons are generated for the integrated circuit design;

1 more element

Dependencies are inferred from the claim text.

System and method of generating integrated circuit mask data

Life of this patent

System and method of generating integrated circuit mask data

Life of this patent

Abstract

Claims20