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US 6,665,206 B2Granted
Array architecture for depletion mode ferroelectric memory devices
AssigneeMicron Technology, Inc.
InventorCraig T. Salling
Life of this patent
Estimating the term…
Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments have an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Claims18
A memory array, comprising:
- a plurality of ferroelectric floating-gate memory cells arranged in rows and columns;
- a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level;
- a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level;
- and
- a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level;
- wherein each program line is isolated from and orthogonal to each word line;
- wherein each bit line is isolated from and parallel to each program line;
- wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells;
- and
- wherein each program line is laterally offset from its associated bit line.
7 more elements
A memory device, comprising:
- an array of memory cells having a plurality of ferroelectric floating-gate memory cells arranged in rows and columns;
- a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level;
- a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level;
- and
- a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level;
- wherein each program line is isolated from and orthogonal to each word line;
- wherein each bit line is isolated from and parallel to each program line;
- wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells;
- and
- wherein each program line is laterally offset from its associated bit line.
7 more elements
An electronic system, comprising:
- a processor;
- and
- a memory device coupled to the processor, the memory device comprising:
- an array of memory cells having a plurality of ferroelectric floating-gate memory cells arranged in rows and columns;
- a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level;
- a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level;
- and
- a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level;
- wherein each program line is isolated from and orthogonal to each word line;
- wherein each bit line is isolated from and parallel to each program line;
- wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells;
- and
- wherein each program line is laterally offset from its associated bit line.
10 more elements
Dependencies are inferred from the claim text.