US 6,664,603 B2Granted

Semiconductor device, memory system and electronic apparatus

AssigneeSeiko Epson Corporation

InventorsJunichi Karasawa, Kunio Watanabe

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Abstract

A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L1 between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L2 between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

Claims15

Dependent claims

A semiconductor device having a memory cell including a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor, the semiconductor device comprising:

a first gate-gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor;
and
a first drain-gate wiring layer that is continuous with the first gate-gate electrode layer, provided in a manner to extend in a direction transverse to the first gate-gate electrode layer, and provided at least between an active region for the first load transistor and an active region for the first driver transistor,
wherein a distance L1 between the edges of the first drain-gate wiring layer and the active region for the first driver transistor is greater than or equal to a distance L2 between the edges of the first drain-gate wiring layer and the active region for the first load transistor.

1 more element

a first gate-gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor;
a second gate-gate electrode layer including a gate electrode of the second load transistor and a gate electrode of the second driver transistor;
a first drain-gate wiring layer that is continuous with the first gate-gate electrode layer, provided in a manner to extend in a direction transverse to the first gate-gate electrode layer, and provided at least between an active region for the first load transistor and an active region for the first driver transistor;
and
a contact pad layer that is continuous with the second gate-gate electrode layer, provided in a manner to extend in a direction transverse to the second gate-gate electrode layer, and provided between an active region for the second load transistor and an active region for the second driver transistor,
wherein a distance L1 between the edges of the first drain-gate wiring layer and the active region for the first driver transistor is substantially equal to a distance L3 between the edges of the contact pad layer and the active region for the second driver transistor is L3.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/153,430Filed 21 May 2002
Priority: JP 2001-15511424 May 2001
Published: US 2002/0190330 A119 Dec 2002
Granted: 16 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
Y10S 257/903
Active solid-state devices, e.g. transistors, solid-state diodes: fET configuration adapted for use as static memory cell
H10B
Electronic memory devices
Y10S
Technical subjects covered by former uspc cross-reference art collections [xracs] and digests