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US 6,664,584 B2Granted
Metal oxynitride capacitor barrier layer
AssigneeMicron Technology, Inc.
InventorsSam Yang, Vishnu K. Agrawal
Life of this patent
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Abstract
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
Claims18
A memory device, comprising:
- an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising:
- a bottom electrode having a bottom electrode metal component;
- a top electrode having a top electrode metal component;
- a dielectric layer interposed between the bottom electrode and the top electrode;
- and
- at least one metal oxynitride barrier layer having a baffler metal component, wherein the baffler metal component is different from the bottom electrode metal component or wherein the baffler metal component is different from the top electrode metal component, wherein the at least one metal oxynitride barrier layer is interposed between the dielectric layer and the bottom electrode or wherein the at least one metal oxynitride layer is interposed between the dielectric layer and the top electrode;
- a row access circuit coupled to the array of memory cells;
- a column access circuit coupled to the array of memory cells;
- and
- an address decoder circuit coupled to the row access circuit and the column access circuit.
7 more elements
A memory device, comprising:
- an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising:
- a bottom electrode having a bottom electrode metal component;
- a top electrode having a top electrode metal component;
- a dielectric layer interposed between the bottom electrode and the top electrode;
- and
- at least one tungsten oxynitride baffler layer having a baffler metal component, wherein the baffler metal component is different from the bottom electrode metal component or wherein the baffler metal component is different from the top electrode metal component, wherein the at least one tungsten oxynitride barrier layer is interposed between the dielectric layer and the bottom electrode or wherein the at least one tungsten oxynitride layer is interposed between the dielectric layer and the top electrode;
- a row access circuit coupled to the array of memory cells;
- a column access circuit coupled to the array of memory cells;
- and
- an address decoder circuit coupled to the row access circuit and the column access circuit.
7 more elements
A memory device, comprising:
- an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising:
- a bottom electrode having a bottom electrode metal component;
- a top electrode having a top electrode metal component;
- a metal oxide dielectric layer interposed between the bottom electrode and the top electrode;
- and
- at least one tungsten oxynitride barrier layer having a barrier metal component, wherein the barrier metal component is different from the bottom electrode metal component or wherein the baffler metal component is different from the top electrode metal component, wherein the at least one tungsten oxynitride baffler layer is interposed between the dielectric layer and the bottom electrode or wherein the at least one tungsten oxynitride layer is interposed between the dielectric layer and the top electrode;
- a row access circuit coupled to the array of memory cells;
- a column access circuit coupled to the array of memory cells;
- and
- an address decoder circuit coupled to the row access circuit and the column access circuit;
- wherein one of the bottom and top electrodes comprises a metal nitride.
8 more elements
A memory device, comprising:
- an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising:
- a top electrode having a top electrode metal component and a bottom electrode having a bottom electrode metal component;
- a dielectric layer comprising at least one metal oxide separating the bottom and top electrodes;
- at least one metal oxynitride barrier layer arranged between the dielectric layer and one of the top and bottom electrodes, wherein the at least one metal oxynitride barrier layer having a barrier metal component, wherein the barrier metal component is different from the bottom electrode metal component or wherein the barrier metal component is different from the top electrode metal component;
- a row access circuit coupled to the array of memory cells;
- a column access circuit coupled to the array of memory cells;
- and
- an address decoder circuit coupled to the row access circuit and the column access circuit.
5 more elements
Dependencies are inferred from the claim text.