Pre STI-CMP planarization scheme

A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising:

• depositing a polish stop layer on the surface of a substrate;
• depositing an etch stop layer overlying said polish stop layer;
• etching a plurality of isolation trenches through said etch stop layer and said polish stop layer into said substrate whereby narrow active areas and wide active areas of said substrate are left between said isolation trenches;
• depositing by a high density plasma process an oxide layer over said etch stop layer and within said isolation trenches;
• thereafter covering said oxide layer with a mask in said narrow active areas and in said isolation trenches and etching away said oxide layer in said wide active areas stopping at said etch stop layer;
• and
• thereafter removing said mask and polishing away said etch stop layer to said polish stop layer whereby said oxide layer in said isolation trenches is planarized to complete planarized said shallow trench isolation regions in said manufacture of said integrated circuit device.

A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising:

• depositing a pad oxide layer on the surface of a substrate;
• depositing a polish stop layer overlying said pad oxide layer;
• depositing an etch stop layer overlying said polish stop layer wherein said etch stop layer is selected from the group consisting of polysilicon and amorphous silicon;
• etching a plurality of isolation trenches through said etch stop layer and said polish stop layer into said substrate whereby narrow active areas and wide active areas of said substrate are left between said isolation trenches;
• growing a liner layer within said isolation trenches whereby an outside portion of said etch stop layer is also oxidized;
• depositing by a high density plasma process an oxide layer over said etch stop layer and over said liner layer within said isolation trenches;
• removing an upper portion of said oxide layer using a wet dip;
• thereafter covering said oxide layer with a mask in said narrow active areas and in said isolation trenches and etching away said oxide layer in said wide active areas stopping at said etch stop layer wherein said mask is a photoresist mask formed using a reverse mask process;
• and
• thereafter removing said mask and polishing away said etch stop layer to said polish stop layer whereby said oxide layer in said isolation trenches is planarized to complete planarized said shallow trench isolation regions in said manufacture of said integrated circuit device.