Dielectric ARC scheme to improve photo window in dual damascene process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKwang-Ming Lin, Chung-Hung Lu, Szu-An Wu, Ya-Li Tai, Kun-Yi Liu
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Abstract
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective coating, DARC, comprised of multiple layers of silicon oxynitride, SiON, with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.
Claims31
A method of improving photolithography patterning process in a damascene process, by use of anti-reflective coating layers, the method comprising:
- forming an etch-stop layer over an underlying semiconductor substrate that contains integrated circuit elements or over a metal layer;
- forming an intermetal dielectric layer over the etch-stop layer;
- forming a first anti-reflection coating layer on the intermetal dielectric layer;
- forming a second anti-reflection coating layer on the first anti-reflection coating layer;
- forming a layer of photoresist on the second anti-reflection coating layer;
- exposing selected regions of the photoresist layer to ultraviolet light using a photo mask to form exposed regions and unexposed regions;
- removing the exposed selected regions of the photoresist layer by developing, thus providing a patterned photoresist mask for subsequent selective removal of exposed regions of the first and second anti-reflection coating layers, and for subsequent selective removal of exposed regions of the intermetal dielectric layer forming a via opening.
A method of improving photolithography patterning process in a dual damascene process to improve the processing window by use of anti-reflective coating layers, the method comprising:
- forming an etch-stop layer of silicon nitride over an underlying semiconductor substrate that contains integrated circuit elements;
- forming an intermetal dielectric layer of fluorine doped poly-silicon glass over the etch-stop layer;
- forming a first anti-reflection coating layer of silicon oxynitride, bottom layer, on the intermetal dielectric layer;
- forming a second anti-reflection coating layer of silicon oxynitride, top layer, on the first anti-reflection coating layer;
- forming a layer of via photoresist on the second anti-reflection coating layer;
- exposing selected regions of the via photoresist layer to ultraviolet light using a via photo mask to form exposed regions and unexposed regions;
- removing the exposed selected regions of the via photoresist layer by developing and providing a patterned via photoresist mask for subsequent selective removal of exposed regions;
- removing exposed regions of the first and second anti-reflection coating layers;
- removing exposed regions of the intermetal dielectric layer to form via openings;
- stripping the via photoresist;
- forming a layer of trench photoresist on the second anti-reflection coating layer;
- exposing selected regions of the trench photoresist layer to ultraviolet light using a trench photo mask to form exposed regions and unexposed regions;
- removing the exposed selected regions of the trench photoresist layer by developing and providing a patterned trench photoresist mask for subsequent selective removal of exposed regions;
- removing exposed regions of the first and second anti-reflection coating layers;
- removing exposed regions of the intermetal dielectric layer to form trench openings and trench/via openings;
- stripping the trench photoresist;
- filling the trench/via openings with metal;
- removing the excess metal on the surface and planarizing the surface to form inlaid metal interconnect lines and contact vias, in a dual damascene process.
A method of improving photolithography patterning process in a dual damascene process to improve the photolithography processing window by use of anti-reflective coating layers with an exposure wavelength of 248 nanometers, the method comprising:
- forming an etch-stop layer of silicon nitride over an underlying semiconductor substrate that contains integrated circuit elements;
- forming an intermetal dielectric layer of fluorine doped poly-silicon glass over the etch-stop layer;
- forming a first anti-reflection coating layer of silicon oxynitride, bottom layer, on the intermetal dielectric layer;
- forming a second anti-reflection coating layer of silicon oxynitride, top layer, on the first anti-reflection coating layer;
- forming a layer of 5,000 Angstroms thick via photoresist on the second anti-reflection coating layer;
- exposing selected regions of the via photoresist layer to ultraviolet light, wavelength 248 nanometers, using a via photo lith mask to form exposed regions and unexposed regions;
- removing the exposed selected regions of the via photoresist layer by developing, hardening and this provides a patterned via photoresist mask for subsequent selective removal of exposed regions;
- removing exposed regions of the first and second anti-reflection coating layers;
- removing exposed regions of the intermetal dielectric layer to form via openings;
- stripping the via photoresist;
- forming a layer of 5,000 Angstroms thick trench photoresist on the second anti-reflection coating layer;
- exposing selected regions of the trench photoresist layer to ultraviolet light, wavelength 248 nanometers, using a trench photo lith mask to form exposed regions and unexposed regions;
- removing the exposed selected regions of the trench photoresist layer by developing, hardening and this provides a patterned trench photoresist mask for subsequent selective removal of exposed regions;
- removing exposed regions of the first and second anti-reflection coating layers;
- removing exposed regions of the intermetal dielectric layer to form trench openings and trench/via openings;
- stripping the trench photoresist;
- filling the trench/via openings with copper metal;
- removing the excess copper metal on the surface and planarizing the surface to form inlaid copper metal interconnect lines and contact vias.
Dependencies are inferred from the claim text.