Ferroelectric memory configuration and a method for producing the configuration

A method for producing an integrated ferroelectric memory configuration, which comprises:

• configuring memory cells using a stacking principle;
• for each one of the memory cells, providing a capacitor having two capacitor electrodes located one above another and providing an associated selection transistor located in a substrate below the capacitor;
• for each one of the memory cells, providing contact plugs to directly electrically connect the two capacitor electrodes to a source region and a drain region of the associated selection transistor;
• producing given ones of the contact plugs from above;
• in a first step, for the capacitor of each one of the memory cells, first producing one of the contact plugs for a lower one of the capacitor electrodes and then producing a dielectric;
• in a second step, for the capacitor of each one of the memory cells, etching a contact hole from above, through the upper one of the capacitor electrodes and at least through the dielectric as far as a substrate area of the associated selection transistor, the contact hole being for one of the given ones of the contact plugs for contact connecting an upper one of the capacitor electrodes;
• and
• in a third step, for the capacitor of each one of the memory cells, producing the one of the given ones of the contact plugs from above by filling the contact hole with a highly conductive metallic material to form an electrically conductive connection between the upper one of the capacitor electrodes and the substrate area of the associated selection transistor.