Method of forming metal fuses in CMOS processes with copper interconnect
AssigneeLSI Logic Corporation
InventorsRuggero Castagnetti, Prabhakar Pati Tripathi, Ramnath Venkatraman
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Abstract
The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.
Claims21
A method of forming a semiconductor device fuse, the method comprising:
- depositing a first passivation layer on a patterned top-most metal layer in a semiconductor device;
- patterning and etching the first passivation layer to provide access to at least two fuse contacts located in the top-most metal layer;
- depositing a conductive pad metal layer on the patterned first passivation layer;
- patterning and etching the conductive pad metal layer to form a metal fuse region connecting the at least two fuse contacts;
- and
- depositing a second passivation layer on the patterned conductive layer.
A method of forming a semiconductor device fuse, the method comprising:
- depositing a first passivation layer on a patterned interconnect metal layer in a semiconductor device;
- patterning and etching the first passivation layer to form at least two contact holes;
- depositing a conductive pad metal layer on the patterned first passivation layer and filling the at least two contact holes;
- patterning and etching the conductive pad metal layer to form a metal fuse region in the conductive pad metal layer, wherein the metal fuse region is electrically connected to the at least two conductive metal lines located in the patterned interconnect metal layer and wherein the at least two filled contact holes form at least part of the electrical path between the metal fuse region and the at least two conductive metal lines;
- and
- depositing a second passivation layer on the patterned and etched conductive pad metal layer.
Dependencies are inferred from the claim text.