US 6,661,722 B2Granted

Layout method for bit line sense amplifier driver

AssigneeSamsung Electronics Co., Ltd.

InventorsJae-young Lee, Jong-hyun Choi

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Abstract

A bit line sense amplifier is provided. The bit line sense amplifier includes a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out, and first drivers, which are arranged outside the plurality of first sense amplifiers, for pulling down the bit line or the complementary bit line to a first voltage level. The bit line sense amplifier further includes a second sense amplifier block with a plurality of second sense amplifiers and second drivers for pulling up the bit line or the complementary bit line to a second voltage level. By arranging the drivers outside the bit sense amplifiers, effects caused by variation in critical dimensions (CDs) of gates are minimized and the entire area of the bit line sense amplifier is reduced.

Claims8

Dependent claims

A bit line sense amplifier comprising:

a sense amplifier block in which a plurality of sense amplifiers for sensing and amplifying data of a memory cell are laid out, each sense amplifier including a pair of transistors;
and
drivers corresponding to each of the plurality of sense amplifiers which are laid out outside the plurality of sense amplifiers allowing a distance between pates of the pair of transistors for each of the plurality of sense amplifiers to be equalized, for transmitting a first power supply to each of the sense amplifiers in response to a control signal;
wherein each of the drivers comprises:
a global power supply transmission line for supplying the first power supply, which is laid out in a first direction;
a local power supply transmission line which is laid out in a second direction and connected to the global power supply transmission line at 90 degrees;
and
a via which is connected between the global power supply transmission line and the local power supply transmission line;
wherein the first power supply is supplied to each of the sense amplifiers through the global power supply transmission line and the local power supply transmission line.

6 more elements

A bit line sense amplifier comprising:

a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out;
and
first drivers for pulling down the bit line or the complementary bit line to a first voltage level, which is lower than a pre-charge voltage in response to a first control signal;
wherein each of the first drivers is arranged outside the plurality of first sense amplifiers.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 10/190,652Filed 8 Jul 2002
Priority: KR 2001-4379020 Jul 2001
Published: US 2003/0016059 A123 Jan 2003
Granted: 9 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G11C 7/065
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of latching type
H10D
Inorganic electric semiconductor devices
G11C
Static stores