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US 6,661,705 B1Granted
Low voltage flash EEPROM memory cell with improved data retention
AssigneeAgere Systems Inc.
InventorsRichard J. McPartland, Ranbir Singh
Life of this patent
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Abstract
The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.
Claims14
A method of fabricating a memory cell, comprising
- forming a control input;
- forming a switch;
- and
- forming a voltage transfer structure, including:
- forming a linear capacitor that electrically couples the control input to the switch, wherein forming said linear capacitor has an overlap capacitance substantially greater than a capacitance of the switch.
2 more elements
A method of fabricating an integrated circuit having an programmable read-only-memory (PROM), comprising:
- forming transistors;
- forming memory cells with at least one of the memory cells including:
- forming a voltage transfer structure, including:
- forming a linear capacitor that electrically couples the control input to the switch;
- and
- forming interconnects that electrically connect the transistors and the memory cells to form an operative integrated circuit.
3 more elements
Dependencies are inferred from the claim text.