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US 6,661,701 B2Granted
Three-transistor DRAM cell and associated fabrication method
AssigneeInfineon Technologies AG
InventorsClaus Dahl, Siegmar Köppe
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Abstract
The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer are additionally formed on a gate layer of the memory transistor. A substantially constant voltage value is present between a potential of the conductive layer and a potential of the substrate area. A three-transistor DRAM cell with improved interference immunity and charge retention time
Claims10
A three-transistor DRAM cell, comprising:
- a memory transistor for dynamically storing information;
- a write transistor connected for writing information to said memory transistor;
- and
- a read transistor connected for reading information from said memory transistor;
- said memory transistor being a field-effect transistor having a substrate area, a first insulating layer above said substrate area, a gate layer above said insulating layer formed with a short-channel section and a long-channel section, a second insulating layer and a conductive layer;
- and
- said second insulating layer formed directly on said gate layer;
- and
- said conductive layer formed on said second insulating layer;
- said conductive layer connected to a potential and said substrate area connected to a potential such that a potential difference between the potential on said conductive layer and the potential on said substrate area is substantially constant.
7 more elements
Dependencies are inferred from the claim text.