Semiconductor memory device

Abstract

A semiconductor memory device of the present invention has a memory array structure wherein a plurality of word lines and a plurality of bit lines for selecting a predetermined memory cell are arranged to intersect with one another, and includes two memory cells (e.g., MC1 and MC2) constituting one bit and a sense amplifier electrically connected to the both memory cells through the bit lines. The word line (e.g., WL3A) electrically connected to one (e.g., MC1) of the two memory cells constituting one bit and the word line (e.g., WL3B) electrically connected to the other memory cell (e.g., MC2) are arranged opposite each other across the sense amplifier. Thus, a twin-cell type semiconductor memory device capable of reducing a plane area occupied by a memory cell part while maintaining good retention characteristics.

Dependencies are inferred from the claim text.