US 6,661,060 B2Granted

Low capacitance ESD protection device

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJian-Hsing Lee, Kuo-Reay Peng, Shih-Chyi Wong

Life of this patent

Estimating the term…

Loading patent…

Abstract

An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N+ diffusion) next to the it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion) is located on either side of each source (N+ diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P+ diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

Claims23

Dependent claims

A low capacitance electrostatic discharge (ESD) protection device, comprising:

a) a circuit pad which receives an ESD and couples said ESD into said protection device;
b) a semiconductor wafer with a P-substrate;
c) a reference potential;
d) a first and a second NMOS transistor disposed in said P-substrate, said first and said second NMOS transistor each comprising a gate, an N+ diffusion source and drain, said NMOS transistors symmetrically arranged;
e) an N-well deposited in said P-substrate between the drains of said first and said second NMOS transistor, where the junction capacitance of said N-well of less than 0.035 pF is much less than the combined junction capacitance of the drains of said NMOS transistors;
f) a first P+ diffusion disposed in close proximity to said source of said first NMOS transistor, said first P+ diffusion connected to said reference potential;
g) a second P+ diffusion disposed beyond the source of said second NMOS transistor, said second P+ diffusion connected to said reference potential;
h) a third P+ diffusion disposed in said N-well, said third P+ diffusion connected to said circuit pad;
i) a diode comprised of said third P+ diffusion and said N-well;
j) a first parasitic silicon controlled rectifier (SCR) connected between said third P+ diffusion and said source of said first NMOS transistor, said first SCR comprising a first parasitic pnp transistor, and a first and a second parasitic npn transistor, said first SCR providing a first current path for said ESD voltage;
and
k) a second parasitic SCR connected between said third P+ diffusion and said source of said second NMOS transistor, said second SCR comprising said first parasitic pnp transistor, and a third and a fourth parasitic npn transistor, said second SCR providing a second current path for said ESD voltage.

9 more elements

A low capacitance electrostatic discharge (ESD) protection device, comprising:

a circuit pad which receives ESD pulses and couples said ESD pulses into said protection device;
a semiconductor wafer with a P-substrate;
a reference potential;
a first and a second N+ diffusion deposited in said P-substrate, said first and said second N+ diffusion having a combined junction capacitance ranging from 0.01 pF to 1 pF;
diffusing an N-well into said P-substrate, where the junction capacitance of said N-well of less than 0.035 pF is much smaller than said combined junction capacitance of said first and said second N+ diffusion;
a third N+ diffusion deposited in said P-substrate, said third N+ diffusion separated from said first N+ diffusion by a first gate, where said first and said third N+ diffusion are the drain and source of a first NMOS transistor, respectively;
a fourth N+ diffusion deposited in said P-substrate, said fourth N+ diffusion separated from said second N+ diffusion by a second gate, where said second and said fourth N+ diffusion are the drain and source of a second NMOS transistor, respectively;
a first P+ diffusion disposed in close proximity to said source of said first NMOS transistor;
a second P+ diffusion disposed on the other side of said source of said second NMOS transistor, said first and said second P+ diffusion together acting as a guard ring for said first and said second NMOS transistor;
a third P+ diffusion disposed in said N-well;
said first and said second N+ diffusion and said third P+ diffusion coupled to said circuit pad;
said third and said fourth N+ diffusion and said first and said second P+ diffusion coupled to said reference potential;
a diode comprised of said third P+ diffusion and said N-well;
a first parasitic silicon controlled rectifier (SCR) connected between said third P+ diffusion and said third N+ diffusion, said first SCR further comprising:
a first parasitic pnp transistor having an emitter, a base, and a collector, wherein said emitter is said third P+ diffusion, said base is said N-well, and said collector is said P-substrate
a first parasitic npn transistor having an emitter, a base, and a collector, wherein said emitter and said collector are said source and the drain of said first NMOS transistor, respectively, and said base is said P-substrate;
a second parasitic npn transistor having an emitter, a base, and a collector, wherein said emitter is said source of said first NMOS transistor, said collector is said N-well, and said base is said P-substrate;
a first bulk resistor connected between said N-well and said first P+ diffusion;
a second parasitic SCR connected between said third P+ diffusion and said fourth N+ diffusion, said second SCR further comprising:
said first parasitic pnp transistor;
a first parasitic npn transistor having an emitter, a base, and a collector, wherein said emitter and said collector are said source and the drain of said second NMOS transistor, respectively, and said base is said P-substrate;
a second parasitic npn transistor having an emitter, a base, and a collector, wherein said emitter is said source of said second NMOS transistor, said collector is said N-well, and said base is said P-substrate;
and
a second bulk resistor connected between said N-well and said second P+ diffusion.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/213,613Filed 7 Aug 2002 · division
Priority: 20 Feb 2001
Published: US 2002/0187601 A112 Dec 2002
Granted: 9 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10D 89/601
Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]:…
H10D 84/811
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: combinations of…
H10D
Inorganic electric semiconductor devices