Memory cell with trench transistor

A memory cell with a storage transistor, comprising:

• a semiconductor body having a top surface and a trench formed therein with walls joined by a curved bottom having a lowest point;
• a source zone in said semiconductor body doped from said top surface;
• a junction of said source zone beneath said source zone;
• a drain zone in said semiconductor body doped from said top surface;
• a junction of said drain zone beneath said drain zone;
• a gate electrode on said top surface of said semiconductor body being disposed between said source zone and said drain zone in said trench;
• a dielectric layer isolating said gate electrode from said semiconductor body an acting as a storage medium;
• said junctions intersecting a respective one of said walls at a height from said lowest point;
• a spacing being defined between said junctions across said trench;
• and
• said height being no larger than one half said spacing.

A memory cell with a storage transistor, comprising:

• a semiconductor body having a top surface and a trench formed therein having walls joined by a curved bottom, said curved bottom having a minimum radius;
• a source zone in said semiconductor body doped from said top surface;
• a junction of said source zone beneath said source zone;
• a drain zone in said semiconductor body doped from said top surface;
• a junction of said drain zone beneath said drain zone;
• a gate electrode on said top surface of said semiconductor body being disposed between said source zone and said drain zone in said trench;
• a dielectric layer isolating said gate electrode from said semiconductor body and acting as a storage medium;
• each of said junctions intersecting a respective one of said walls at a respective depth;
• and
• each of said walls having a respective curve radius at each respective depth of said junctions being at most ten percent larger than said minimum radius of said curved bottom.

A memory cell with a storage transistor, comprising

• a semiconductor body having a top surface and a trench formed therein having walls joined by a curved bottom, said trench having a longitudinal direction;
• a source zone in said semiconductor body doped from said top surface;
• a junction of said source zone beneath said source zone;
• a drain zone in said semiconductor body doped from said top surface;
• a junction of said drain zone beneath said drain zone;
• a gate electrode on aid top surface of said semiconductor body being disposed between said source zone and said drain zone in said trench;
• a dielectric layer isolating said gate electrode from said semiconductor body and including boundary layers and a storage layer for holding charge carriers separating said boundary layers;
• and
• a region of said storage layer being neutralized during an erase operation by a electrical field having a component aligned parallel to tangent of at least one of said walls and said bottom and perpendicular to the longitudinal direction;
• each of said junctions intersecting a respective one of said walls at a respective depth from said bottom;
• and
• said depth of said trench being set to maximize the component of the electric field at said region.