US 6,661,043 B1 · One-transistor RAM approach for high density memory application

Abstract

A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.

Claims61

Dependent claims

A method for the creation of a 1T RAM cell, comprising the steps of:

providing a substrate, a layer of pad oxide having been provided over the substrate, a first layer of etch stop material having been provided over the pad oxide;
etching at least one trench having a first surface area through the first layer of etch stop material, through the layer of pad oxide and into the surface of the substrate;
creating a second layer of etch stop material over surfaces of the at least one trench;
filling the at least one trench with a layer of insulation material to a level of the surface of the first layer of etch stop material;
removing the layer of insulation material to a depth over a second surface area being smaller than the first surface area, creating a third surface area of the layer of insulation material above which the layer of insulating material has been removed being larger than the second surface area, exposing the second layer of etch stop material;
removing the layers of first etch stop material, pad oxide and the exposed second layer of etch stop material;
creating a layer of capacitor dielectric over the third surface area of the layer of insulating material and extending adjacent thereto;
and
creating a layer of capacitor material over the layer of capacitor dielectric material.

6 more elements

A method for the creation of a 1T RAM cell, comprising the steps of:

providing a substrate;
growing a layer of pad oxide over the surface of the substrate;
depositing a first layer of etch stop material over the layer of pad oxide;
etching at least one trench having a first surface are through the first layer of etch stop material, through the layer of pad oxide and into the surface of the substrate;
performing an N2 impurity implant into exposed surfaces of the at least one trench;
growing a layer of liner oxide over exposed surfaces of the at least one trench, creating a second layer of etch stop material over exposed surfaces of the at least one trench;
depositing a layer of insulating material over the surface of the first layer of etch stop material, including the surface of the layer of liner oxide;
planarizing the layer of insulating material to about the surface of the first layer of etch stop material, creating at least one layer of insulating material having a first surface area;
providing a crown etch mask over the surface of the first layer of insulating material, including the surface of the at least one layer of insulating material, exposing the at least one layer of insulating material over a second surface area being smaller than the first surface area;
etching the at least one layer of insulating material in accordance with the crown etch mask, creating a third surface area of the at least one layer of insulating material being larger than the second surface area, exposing the second layer of etch stop material;
removing the crown etch mask, the first layer of etch stop material, the layer of pad oxide and the exposed second layer of etch stop material;
creating a layer of capacitor dielectric over the third surface area of the at least one layer of insulating material and extending adjacent thereto;
and
creating a layer of capacitor material over the surface of the layer of capacitor dielectric material.

11 more elements

A method for the creation of a 1T RAM cell, comprising the steps of:

providing a substrate;
growing a layer of pad oxide over the surface of the substrate;
depositing a first layer of etch stop material over the layer of pad oxide;
etching at least one trench having a first surface are through the first layer of etch stop material, through the layer of pad oxide and into the surface of the substrate;
creating a compound layer over exposed surfaces of the at least one trench, comprising:
(i) growing a layer of liner oxide over exposed surfaces of the at least one trench;
and
(ii) depositing a layer of silicon nitride over the layer of liner oxide, creating a second layer of etch stop material over exposed surfaces of the at least one trench;
depositing a layer of insulating material over the surface of the first layer of etch stop material, including the surface of the layer of silicon nitride;
planarizing the layer of insulating material to about the surface of the first layer of etch stop material, creating at least one layer of insulating material having a first surface area;
providing a crown etch mask over the surface of the first layer of insulating material, including the surface of the at least one layer of insulating material, exposing the at least one layer of insulating material over a second surface area being smaller than the first surface area;
etching the at least one layer of insulating material in accordance with the crown etch mask, creating a third surface area of the at least one layer of insulating material being larger than the second surface area, exposing the first layer of etch stop material and the compound layer;
removing the crown etch mask, the first layer of etch stop material, the layer of pad oxide and the exposed compound layer;
creating a layer of capacitor dielectric over the third surface area of the at least one layer of insulating material and extending adjacent thereto;
and
creating a layer of capacitor material over the surface of the layer of capacitor dielectric material.

13 more elements

A structure a damage-free surface of a capacitor in a 1T-RAM cell, comprising:

n/p well surface areas in the surface of the substrate defined by providing n/p-type impurity implants into the surface of a substrate;
cell well surface areas defined in the surface of the substrate by providing impurity implants into the surface of a substrate;
at least one trench created in the surface of the substrate;
a layer of etch stop material, comprising SION, created over exposed surfaces of the at least one trench by first N2 ion implantation into exposed surfaces of the at least one trench and second growing a layer of liner oxide over inside surfaces of said at least one trench;
the at least one trench having been filled with insulating material having a first surface area, the insulating material extending over the at least one trench by a height;
capacitor areas having been defined over the insulating material by patterning and etching the layer of insulating material over a second surface area being smaller than the first surface area to a depth, creating a third surface area of the layer of insulating material above which the layer of insulating material has been removed, the third surface area being larger than the second surface area, exposing the layer of SiON, the exposed layer of SiON having been removed;
a layer of gate oxide having been created over the surface of the substrate;
a layer of gate material having been deposited over the surface of the layer of gate oxide;
the layers of gate oxide and gate material having been patterned and etched, simultaneously creating layers of gate oxide, gate electrode material, capacitor dielectric and upper capacitor plates;
and
gate electrodes having been completed over the surface of the substrate, including conductive interconnects to the gate electrodes and the upper capacitor plates.

8 more elements

A structure a damage-free surface of a capacitor in a 1T-RAM cell, comprising:

n/p well surface areas in the surface of the substrate defined by providing n/p-type impurity implants into the surface of a substrate;
cell well surface areas defined in the surface of the substrate by providing impurity implants into the surface of a substrate;
at least one trench created in the surface of the substrate;
a layer of etch stop material, created over exposed surfaces of the at least one trench by first growing a layer of liner oxide over exposed surface of the at least one trench and second depositing a layer of silicon nitride over inside surfaces of said at least one trench;
the at least one trench having been filled with insulating material having a first surface area, the insulating material extending over the at least one trench by a height;
capacitor areas having been defined over the insulating material by patterning and etching the layer of insulating material over a second surface area being smaller than the first surface area to a depth, creating a third surface area of the layer of insulating material above which the layer of insulating material has been removed, the third surface area being larger than the second surface area, exposing the layer of silicon nitride, the exposed layer of silicon nitride having been removed;
a layer of gate oxide having been created over the surface of the substrate;
a layer of gate material having been deposited over the surface of the layer of gate oxide;
the layers of gate oxide and gate material having been patterned and etched, simultaneously creating layers of gate oxide, gate electrode material, capacitor dielectric and upper capacitor plates;
and
gate electrodes having been completed over the surface of the substrate, including conductive interconnects to the gate electrodes and the upper capacitor plates.

8 more elements

Dependencies are inferred from the claim text.

One-transistor RAM approach for high density memory application

Life of this patent

One-transistor RAM approach for high density memory application

Life of this patent

Abstract

Claims61