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US 6,661,041 B2Granted
Digitline architecture for dynamic memory
AssigneeMicron Technology, Inc.
InventorBrent Keeth
Life of this patent
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Abstract
A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross-point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.
Claims23
A semiconductor device comprising:
- a substrate;
- a multi-level digitline pair located on a portion of the substrate, the multi-level digitline pair including a vertical twist at a location on the substrate, the multi-level digitline pair having a first digitline and second digitline thereof vertically offset and vertically aligned on each side of the vertical twist at the location on the substrate, the vertical twist of the multi-level digitline pair at the location on the substrate including:
- the first digitline located below the second digitline on one horizontal side of the vertical twist and located above the second digitline as an upper digitline on an opposite horizontal side of the vertical twist.
An integrated circuit device comprising:
- a substrate having an integrated circuit formed on a portion thereof;
- an integrated circuit die having at least two vertically offset conductive levels;
- and
- a multi-level digitline pair located on a portion of the substrate, the multi-level digitline pair having a first electrically isolated digitline and a second electrically isolated digitline, the multi-level digitline pair including a vertical twist at a location on the substrate;
- each of the first digitline and the second digitline comprising a first section and a second section located in different conductive levels of the at least two vertically offset conductive levels and electrically connected;
- the first digitline and second digitline at the location on the substrate having at least a portion of the first section of the first digitline located vertically above the first section of the second digitline and aligned therewith on one side of the vertical twist and having at least a portion of the second section of the first digitline located vertically below the second section of the second digitline and aligned therewith on another side of the vertical twist.
3 more elements
A dynamic memory device comprising:
- a substrate;
- a multi-level digitline pair located on a portion of the substrate, the multi-level digitline pair having a first digitline and a second digitline vertically offset and aligned at a location on the substrate, the multi-level digitline pair at the location on the substrate undergoing a vertical twist such that the first digitline is located below the second digitline and aligned therewith on one horizontal side of the vertical twist and located above and aligned with the second digitline as an upper digitline on an opposite horizontal side of the vertical twist at the location on the substrate;
- and
- a plurality of addressable memory cells coupled to the multi-level digitline pair such that the plurality of addressable memory cells is coupled to the first digitline and the second digitline when the first digitline and the second digitline are located below another portion of a digitline.
1 more element
Dependencies are inferred from the claim text.