Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating
AssigneeNational University of Singapore
InventorsSam Fong Yau Li, Hou Tee Ng
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Abstract
A novel method for the activation of semiconductor substrates for highly selective electroless copper plating in multilayer interconnect metallization lines and vias/contact holes has been developed. A copper-seeded polysilicon layer is provided over the substrate to facilitate growth of copper into the vias. Subsequent rinsing and chemical-mechanical polishing processes allow removal of overgrowth of copper and the polysilicon layer to achieve overall smooth topography of the copper surface and the insulating layer surface of the substrate.
Claims10
A method of fabrication for a semiconductor integrated circuit device, including:
- providing a semiconductor substrate having an insulating layer with a contact hole formed therein and a diffusion barrier provided on and limited to sidewalls and a base of the hole;
- forming a film of polysilicon on and limited to a surface of the substrate in which the hole is provided;
- subjecting the said substrate to an activation aqueous solution;
- forming an activation layer comprising copper seedings on the said polysilicon;
- rinsing said semiconductor substrate to remove said aqueous solution;
- depositing copper on the activation layer by electroless copper deposition such that the copper forms into said hole to fill the contact hole and thereby provide a plug without voids;
- rinsing said semiconductor substrate;
- and
- applying chemical-mechanical polishing to remove said polysilicon and excess copper external of said hole to thereby provide the substrate with a smooth topography.
Dependencies are inferred from the claim text.