Stand-alone triggering structure for ESD protection of high voltage CMOS
AssigneeNational Semiconductor Corporation
InventorsVladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
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Abstract
In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.
Claims10
A method of forming a NMOS snapback structure with low breakdown voltage, comprising
- forming n+ regions of a source and drain without first forming a lightly doped region, wherein a blocking mask is used to space the n+ drain region from an edge of a gate.
A method of reducing the breakdown voltage of a NMOS device, comprising
- at least partially blocking an NLDD and n+ drain region.
A method of reducing hot carrier degradation in a NMOS device, comprising
- reducing potential differences across junctions near, a gate by keeping the potential difference across the junction between an n+ source and p-well or p-substrate low, and by shifting the junction between an n+ drain and the p-well or p-substrate away from the gate.
A method of reducing the holding voltage of a NMOS device, comprising eliminating at least part of an NLDD to create a drain-substrate junction that is solely between an n+ drain region with its higher injection coefficient and a p-well.
Dependencies are inferred from the claim text.