US 6,660,585 B1Granted

Stacked gate flash memory cell with reduced disturb conditions

AssigneeAplus Flash Technology, Inc.

InventorsPeter W. Lee, Hsing-Ya Tsao, Vei-Han Chan, Hung-Sheng Chen, Fu-Chang Hsu

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Abstract

In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.

Claims1

Dependent claims

A method of producing a stacked gate flash memory cell to reduce disturb conditions, comprising:

a) growing a gate oxide on top of a semiconductor substrate,
b) forming a floating gate on top of said gate oxide,
c) forming an upper oxide layer on top of said floating gate,
d) forming a control gate on top of said floating gate with said upper oxide layer in between to produce a stacked gate,
e) forming an LDD (lightly doped drain) in said substrate only on drain side of said stacked gate using said stacked gate as a mask,
f) forming a source that is heavily doped in said substrate using said stacked gate as a mask,
g) forming sidewall spacers on sides of said stacked gate of an insulating material, then
h) forming a drain that is heavily doped in said substrate using a sidewall spacer located on the sidewalls of the stacked gate as a mask.

5 more elements

Dependencies are inferred from the claim text.