Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devices

A method for providing a bitline contact in an integrated circuit structure, including a substrate with a top surface and a body, a plurality of deep trenches formed in the body with upper and lower sidewalls, with a deep trench capacitor and a gate electrode formed in the deep trenches, the gate electrodes being separated from the body by gate oxide and the deep trench capacitors being separated from the body by capacitor dielectric layers;

• a doped source region juxtaposed with the gate electrodes near the top surface aside from the gate oxide;
• and drain regions formed in the body of the substrate connected to the capacitor, with sidewall spacers between the gate electrodes and the upper sidewalls of the deep trench, the method comprising:
• forming a patterning mask over the device exposing a portion of an upper surface of a gate electrode at the top surface of the substrate, the patterning mask being patterned by the line shaping master mask,
• etching a divot reaching down into the gate electrode alongside a deep trench sidewall spacer juxtaposed with a source region and filling the divot with a dielectric material,
• forming a wordline stack with a wordline and a silicon nitride cap in contact with the gate electrode,
• forming a conformal liner which is etch resistant covering the structure,
• forming a planarized ILD layer covering the conformal liner,
• forming a glass layer covering the planarized ILD layer,
• forming a bitline contact mask patterned by the line shaping master mask, a bitline contact therethrough above the source region juxtaposed with the deep trench sidewall spacer,
• etching a via hole down to the source region in the pattern of the bitline contact mask, and
• forming a bitline contact in the via hole.