BiLevel metallization for embedded back end of the line structures
AssigneeInternational Business Machines Corporation
InventorMichael C. Gaidis
Life of this patent
Estimating the term…
Abstract
MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for good MRAM performance and also for good operation of the logic circuit by setting the standard vertical dimension of the BEOL at the value that is suitable for logic circuits. In the areas where MRAM cells are to be placed, the (N+1)th level is etched separately. A standard etch is applied in logic areas and a deeper etch is applied in MRAM areas, so that the interlevel distance in the logic areas is the standard amount and the interlevel distance is MRAM areas is a lesser amount that is appropriate to accommodate the vertical dimensions of the material layers that go into the MRAM cells.
Claims18
A method of forming an integrated circuit containing a set of MRAM memory elements placed in the BEOL comprising the steps of:
- forming the front end of the integrated circuit;
- forming the first level of interconnect and subsequent levels, including the Nth level of interconnect;
- forming a set of memory elements in a memory region of said integrated circuit, said set of memory elements being in contact with a top surface of said Nth level of interconnect and having a memory cell height;
- depositing the (N+1)th layer of interlevel dielectric with a standard thickness greater than said memory cell height;
- forming logic dual damascene apertures in a logic region of the circuit, said dual damascene apertures in said logic region having a total dual damascene aperture depth sufficient to make contact to the top layer of said Nth level of interconnect and also having a logic interconnect depth, whereby the difference between said memory aperture depth and said logic interconnect depth establishes a logic via depth;
- forming memory damascene apertures in said memory region of the circuit, said memory damascene apertures in said memory region having a memory aperture depth sufficient to make contact to the top surface of said set of memory elements;
- filling both said logic dual damascene apertures and said memory apertures with conductive interconnect material;
- and
- completing said integrated circuit.
A method of forming an integrated circuit containing a set of structures placed in the BEOL comprising the steps of:
- forming the front end of the integrated circuit;
- forming the first level of interconnect and subsequent levels, including the Nth level of interconnect;
- forming a set of structures in at least one separate region of said integrated circuit, said set of structures being in contact with a top surface of said Nth level of interconnect and having a structure height;
- depositing the (N+1)th layer of interlevel dielectric with a standard thickness greater than said structure height;
- forming logic dual damascene apertures in a logic region of the circuit, said dual damascene apertures in said logic region having a total dual damascene aperture depth sufficient to make contact to the top layer of said Nth level of interconnect and also having a logic interconnect depth, whereby the difference between said memory aperture depth and said logic interconnect depth establishes a logic via depth;
- forming structure damascene apertures in said memory region of the circuit, said structure damascene apertures in said memory region having a structure aperture depth sufficient to make contact to the top surface of said set of structures;
- filling both said logic dual damascene apertures and said structure apertures with conductive interconnect material;
- and completing said integrated circuit.
Dependencies are inferred from the claim text.