Test wafer and method for investigating electrostatic discharge induced wafer defects

A method for monitoring severity of electrostatic discharge effects, comprising:

• contacting a test wafer that includes an electrostatic discharge sensitive risk scale geometry formed thereon with a piece of semiconductor manufacturing equipment;
• removing the test wafer from the piece of semiconductor manufacturing equipment;
• and
• analyzing the test wafer using the risk scale geometry to determine severity of any electrostatic discharge effects associated with contact by the piece of semiconductor manufacturing equipment.

A wafer for monitoring electrostatic discharge effects associated with semiconductor manufacturing, comprising:

• a plurality of test modules formed on the wafer;
• a risk scale formed on each test module defined in part by an electrostatic discharge (ESD) sensitive geometry;
• the ESD sensitive geometry including at least one test module defined in part by at least two bodies;
• each body including a surface area sufficient to induce ESD effects;
• and
• a line and a gap disposed between the two bodies.

An apparatus for monitoring electrostatic discharge effects associated with manufacture of an integrated circuit comprising:

• a plurality of test modules with each test module defined in part by a respective electrostatic discharge sensitive geometry;
• the geometry for each test module including at least two bodies;
• each body including sufficient surface area to accommodate an electrostatic discharge;
• a line extending from at least one of the two bodies toward a second of the at least two bodies;
• the line including a terminal end proximate the second body to define a gap between the terminal end and the second body;
• and
• the test modules cooperating with each other to provide an electrostatic discharge sensitive risk scale.