Method and apparatus for performing timing verification of a circuit
AssigneeCompaq Computer Corporation
InventorsNevine Nassif, James Arthur Farrell, Dale Hayward Hall, Gill Watt
Life of this patent
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Abstract
A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.
Claims13
A timing verification system including representation of a circuit comprising:
- load determining means for determining a load corresponding to each of two paths through the at least one DCVSL structure within the circuit;
- delay determining means for determining a path Elmore delay for each of the two paths based upon the determined loads;
- and
- adding means for combining the path Elmore delays for each of the two paths to determine a Elmore delay for the at least one DCVSL structure.
A timing verification system including representation of a circuit comprising:
- means for estimating proportions of a single load discharged through each of two paths through at least one DCVSL structure within the circuit;
- means for determining a load corresponding to each of the two paths, the loads based upon proportions determined by the estimating means;
- means for determining a path Elmore delay for each of the two paths based upon the determined loads;
- and
- means for combining the path Elmore delays for each of the two paths to determine an Elmore delay for the at least one DCVSL structure.
A method of timing verification for a circuit comprising the steps of:
- determining a load corresponding to each of two paths through the at least one DCVSL structure within the circuit;
- determining a path Elmore delay for each of the two paths based upon the determined loads;
- and
- combining the path Elmore delays for each of the two paths to determine a Elmore delay for the at least one DCVSL structure.
A method of timing verification for a circuit comprising the steps of:
- estimating proportions of a single load discharged through each of two paths through at least one DCVSL structure within the circuit;
- determining a load corresponding to each of the two paths, the loads based upon the estimated proportions;
- determining a path Elmore delay for each of the two paths based upon the determined loads;
- and
- combining the path Elmore delays for each of the two paths to determine an Elmore delay for the at least one DCVSL structure.
Dependencies are inferred from the claim text.