Capacitor for highly-integrated semiconductor memory devices and a method for manufacturing the same

A method of fabricating a capacitor in a semiconductor device comprising the steps of:

• preparing a semiconductor substrate;
• forming an insulating interlayer on the semiconductor substrate;
• forming a contact hole through the insulating interlayer;
• forming a contact plug in the contact hole;
• forming a lower electrode, the lower electrode being in electrical contact with the contact plug;
• forming a meta-stable polysilicon layer on a surface of the lower electrode;
• doping the lower electrode with phosphorus at a temperature of 550 to 650° C. in an ambient of phosphorus gas;
• forming a TaON dielectric layer on the lower electrode;
• annealing the TaON dielectric layer;
• and
• forming an upper electrode layer on the TaON dielectric layer.

A method of fabricating a capacitor in a semiconductor device comprising the steps of:

• preparing a semiconductor substrate;
• forming a first insulating interlayer;
• forming a first contact hole through the insulating interlayer to expose a portion of the semiconductor substrate;
• forming a first contact plug in the first contact hole;
• forming an etch barrier layer on an upper surface of the first insulating interlayer and on an upper surface of the contact plug;
• forming a second insulating interlayer on the etch barrier layer;
• forming a hard mask polysilicon layer on the etch barrier layer;
• forming an anti-reflection layer on the hard mask polysilicon layer;
• forming a second contact hole having sidewalls through the anti-reflection layer, the hard mask polysilicon layer, the second insulating interlayer and the etch barrier layer to expose the upper surface of the contact plug;
• forming a doped polysilicon layer on the anti-reflection layer, the sidewalls of the second contact opening, and the exposed upper surface of the contact plug;
• forming a MPS (meta-stable polysilicon) layer on the doped polysilicon layer;
• doping the MPS layer at a temperature of 550 to 660° C. under an ambient of phosphorus gas to form a doped MPS layer;
• forming a sacrificial layer covering the doped MPS layer;
• exposing an upper surface of the second insulating interlayer by selectively removing portions of the sacrificial layer, the MPS layer, the doped polysilicon layer, the anti-reflection layer, and the hard mask polysilicon layer;
• removing completely remaining portions of the sacrificial layer to expose a surface of the remaining portion of the MPS layer;
• forming a TaON dielectric layer on the exposed surface of the second insulating interlayer and the surface of the MPS layer;
• annealing the TaON dielectric layer at a temperature of 700 to 900° under an ambient of N2O or O2;
• forming an upper electrode on the TaON dielectric layer;
• and
• annealing the upper electrode at a temperature of 800 to 950° C.