Semiconductor device having shallow trench isolation structure and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorJoo-Wook Park
Life of this patent
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Abstract
A semiconductor device having a shallow trench isolation (STI) structure, which is capable of reducing leakage current in a P-FET and improving the device characteristics of a memory device, and a manufacturing method thereof, including a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein; a first sidewall oxide layer formed on the inner surface of the first trench; a second sidewall oxide layer, which is thinner than the first sidewall oxide layer, formed on the inner surface of the second trench; a liner formed on the surfaces of the first and second sidewall oxide layers; and a dielectric material that fills the first and second trenches.
Claims29
A method of manufacturing a semiconductor device having an STI structure, comprising:
- forming a first trench and a second trench in selective areas of a semiconductor substrate;
- forming a first sidewall oxide layer on an inner surface of the first trench and a second sidewall oxide layer on an inner surface of the second trench, the second sidewall oxide layer having a thickness less than the first sidewall oxide layer;
- forming a liner on surfaces of the first and second sidewall oxide layers;
- and filling the first and second trenches with a dielectric material,
- wherein forming the first and second sidewall oxide layers comprises:
- forming an initial oxide layer on the inner surfaces of the first and second trenches:
- selectively removing the initial oxide layer in the second trench;
- and
- forming a first sidewall oxide layer and a second sidewall oxide layer by oxidizing the initial oxide layer in the first trench and the inner surface of the second trench.
A method of manufacturing a semiconductor device having an STI structure, comprising:
- providing a semiconductor substrate having core and periphery areas in which a FET and other circuit devices are formed, and a cell area in which a memory device is formed;
- forming a first trench and a second trench in selective portions of the core area, the periphery area, and cell area of the semiconductor substrate;
- forming an initial oxide layer on inner surfaces of the first and second trenches;
- removing the initial oxide layer in the second trench;
- forming first and second sidewall oxide layers on the inner surfaces of the first and second trenches by oxidizing the initial oxide layer in the first trench and the inner surface of the second trench, the second sidewall oxide layer having a thickness less than the first sidewall oxide layer;
- forming a liner on surfaces of the first and second sidewall oxide layers;
- and
- filling the first and second trenches with a dielectric material.
A method of manufacturing a semiconductor device having an STI structure, comprising:
- providing a semiconductor substrate having core and periphery areas in which a P-FET and other circuit devices are formed, and a cell area in which a memory device is formed;
- forming a first trench and a second trench in selective portions of the core area, the periphery area and the cell area of the semiconductor substrate;
- forming a first sidewall oxide layer to a predetermined thickness on inner surfaces of the first and second trenches;
- forming a second sidewall oxide layer by etching the first sidewall oxide layer in the second trench to a predetermined thickness;
- forming a liner on surfaces of the first and second sidewall oxide layers;
- and
- filling the first and second trenches with a dielectric material.
Dependencies are inferred from the claim text.