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US 6,656,647 B2Granted
Method for examining structures on a wafer
AssigneeInfineon Technologies AG
InventorsGuenther Gerstmeier, Frank Richter, Valentin Rosskopf
Life of this patent
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Abstract
In a method for examining structures on a wafer, at least one mask, which is applied on the wafer and is fabricated by exposure processes, is used for fabricating the structures. Test circuits with test structures are placed on the mask in predetermined reference positions. In order to check the structures and/or the exposure processes, electrical parameters of the test circuits are detected and evaluated in a location-dependent manner.
Claims12
A method for examining structures on a wafer, comprising:
- applying at least one mask on the wafer and the mask being fabricated by exposure processes and is used for fabricating the structures;
- forming test circuits on the mask in predetermined reference positions, forming the test circuits with test transistors having test structures including gate oxide regions, source/drain regions and deep trench regions;
- and
- detecting and evaluating in a location-dependent manner electrical parameters of the test circuits for evaluating the structures and the exposure processes.
1 more element
Dependencies are inferred from the claim text.