Semiconductor integrated circuit device and manufacturing method thereof

A semiconductor integrated circuit device comprising a semiconductor substrate having a surface and an array of memory cells each including a serial combination of a cell selecting transistor and a data storage capacitive element with first and second electrodes as insulatively laminated over each other, the transistor including a metal insulator semiconductor field effect transistor (MISFET) having a source, a drain and an insulated gate electrode, comprising:

• first and second word lines insulatively arranged on the surface of the substrate in a first direction, each having a part forming the gate electrode of the MISFET;
• first and second bit lines insulatively arranged on the surface of the substrate in a second direction transverse to the first direction;
• a conductive strip arranged between the first and second word lines, to electrically connect to one of the source and the drain of the MISFET;
• and
• an insulating film arranged between the conductive strip and the first and second word lines,
• wherein a width of the first and second word lines is larger than a gap between the first and second word lines at a portion of the conductive strip between the first and second bit lines.

A semiconductor integrated circuit device comprising:

• a substrate;
• a memory array including a plurality of metal insulator semiconductor field effect transistors (MISFETs) arranged in a first direction and a second direction transverse to the first direction, each MISFET having a source, a drain and a gate electrode;
• first and second word lines arranged in the first direction, each having a part forming the gate electrode of the MISFET;
• first and second bit lines arranged in the second direction transverse to the first direction;
• a conductive strip arranged between the first and second word lines, to electrically connect the bit lines to one of the source and the drain of the MISFET;
• and
• an insulating film arranged between the conductive strip and the first and second word lines and second bit lines arranged in the second direction,
• wherein a width of the first and second word lines is larger than a gap between the first and second word lines at a portion of the conductive strip between the first and second bit lines.

A semiconductor integrated circuit device comprising:

• word lines extending in a first direction on a principal surface of a substrate;
• bit lines extending in a second direction on the principal surface of the substrate perpendicular to the first direction;
• and
• memory cells disposed at cross points of the word lines and the bit lines, each of said memory cells including a metal insulator semiconductor field effect transistor (MISFET) with a gate electrode as integrally formed with a corresponding one of the word lines, and a capacitive element for information accumulation,
• wherein the word lines extend in the first direction with an identical width, and a distance between adjacent word lines is less than the width of the word lines.