Method of manufacturing a seed layer with annealed region for integrated circuit interconnects
AssigneeAdvanced Micro Devices, Inc.
InventorsKrishnashree Achuthan, Amit P. Marathe
Life of this patent
Estimating the term…
Abstract
A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.
Claims10
A method of manufacturing an integrated circuit comprising:
- providing a semiconductor substrate having a semiconductor device provided thereon;
- forming a dielectric layer on the semiconductor substrate;
- forming an opening in the dielectric layer;
- depositing a barrier layer to line the opening by chemical vapor deposition;
- depositing a seed layer on the barrier layer;
- annealing the seed layer to the barrier layer, the annealing forms an annealed region of under 25% of the thickness of the seed layer;
- depositing a conductor layer over the seed layer to fill the opening and connect to the semiconductor device;
- and
- planarizing the conductor, seed, and barrier layers to be coplanar with the dielectric layer to form a conductor channel therein.
A method of manufacturing an integrated circuit comprising:
- providing a silicon substrate having a semiconductor device provided thereon;
- depositing an oxide layer on the silicon substrate;
- forming an opening in the oxide layer;
- depositing a barrier layer to line the opening by chemical vapor deposition;
- depositing a seed layer on the barrier layer, the annealing forms an annealed region of under 25% of the thickness of the seed layer;
- annealing the seed layer to the barrier layer;
- electroplating a conductor layer using the seed layer to fill the opening and connect to the semiconductor device;
- and
- chemical-mechanical polishing the conductor, seed, and barrier layers to be coplanar with the dielectric layer to form a conductor channel therein.
Dependencies are inferred from the claim text.