Method to form shallow trench isolations
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsSubramanian Balakumar, Kong Hean Lee, Zheng Zhou, Xian Bin Wang
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AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsSubramanian Balakumar, Kong Hean Lee, Zheng Zhou, Xian Bin Wang
Estimating the term…
A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.
A method of forming trenches for shallow trench isolation structures in an integrated circuit device comprising:
A method of forming trenches for shallow trench isolation structures in an integrated circuit device comprising:
A method of forming shallow trench isolations in an integrated circuit device comprising:
Dependencies are inferred from the claim text.