Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor
AssigneeNational Semiconductor Corporation
InventorAbdalla Aly Naem
Life of this patent
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Abstract
A low-power bipolar transistor is formed to have a silicon germanium base region, an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The silicon germanium base region increases the speed of the transistor, while the small extrinsic emitter region reduces the maximum current that can flow through the transistor, and the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.
Claims30
A method for forming a bipolar transistor on a wafer, the wafer having a buried layer, an epitaxial layer of a first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of:
- forming a layer of first isolation material on the epitaxial layer;
- forming a layer of second isolation material on the layer of first isolation material;
- etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to form an exposed region of the epitaxial layer;
- forming a layer of first conductive material on the layers of first and second isolation materials and the exposed region of the epitaxial layer;
- planarizing the layer of first conductive material to form an intrinsic base region surrounded by the layer of first isolation material.
A method for forming a bipolar transistor on a wafer, the wafer having a buried layer, an epitaxial layer of a first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of:
- forming a layer of first isolation material on the epitaxial layer;
- forming a layer of second isolation material on the layer of first isolation material;
- etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to form an exposed region of the epitaxial layer;
- forming a layer of first conductive material on the layers of first and second isolation materials and the exposed region of the epitaxial layer, the layer of first conductive material being silicon germanium, and the layer of first conductive material has a second conductivity type;
- and
- planarizing the layer of first conductive material to form an intrinsic base region surrounded by the layer of first isolation material, the planarizing removing the layer of second isolation material from the layer of first isolation material.
A method for forming a bipolar transistor on a wafer, the wafer having a buried layer, an epitaxial layer of a first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of:
- forming a layer of first isolation material on the epitaxial layer;
- forming a layer of second isolation material on the layer of first isolation material;
- etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to form an exposed region of the epitaxial layer;
- forming a layer of first conductive material on the layers of first and second isolation materials and the exposed region of the epitaxial layer;
- planarizing the layer of first conductive material to form an intrinsic base region surrounded by the layer of first isolation material;
- forming an isolation region on the intrinsic base region;
- forming a layer of second conductive material on the isolation region and the intrinsic base region;
- etching the layer of second conductive material to form an extrinsic emitter on the isolation region and the intrinsic base region;
- etching the isolation region such that a side wall of the extrinsic emitter and a side wall of the isolation region are substantially aligned;
- forming a side-wall spacer on the intrinsic base region to adjoin the extrinsic emitter;
- forming an extrinsic base region in the intrinsic base region after the side-wall spacer has been formed;
- and
- forming an intrinsic emitter region in the intrinsic base region after the extrinsic base region has been formed.
A method of forming a bipolar transistor on a wafer, the wafer having a buried layer of a first conductivity type, and an intermediate layer of the first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of:
- forming a layer of first isolation material on the intermediate layer;
- forming a layer of second isolation material on the layer of first isolation material;
- etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to expose a surface region of the intermediate layer;
- forming a layer of first conductive material on the surface region of the intermediate layer;
- planarizing the layer of first conductive material to form a conductive region surrounded by the layer of first isolation material;
- forming an isolation region on the conductive region;
- forming a layer of second conductive material on the isolation region and the conductive region;
- and
- etching the layer of second conductive material to form an emitter on the isolation region and the conductive region, and expose the conductive region.
A method of forming a bipolar transistor on a wafer, the wafer having a buried layer of a first conductivity type, and an intermediate layer of the first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of:
- forming a conductive region on the intermediate layer;
- forming an isolation region on the conductive region;
- forming a layer of conductive material on the isolation region and the conductive region;
- and
- etching the layer of conductive material to form an emitter on the isolation region and the conductive region, and expose the conductive region.
Dependencies are inferred from the claim text.