Method of planarizing non-volatile memory device

A method of planarizing a semiconductor device comprising the steps of:

• forming a conductive layer on a semiconductor substrate having a first area in which a stacked structure is formed and a second area in which no stacked structure is formed;
• forming a hard mask layer on the conductive layer;
• forming a first insulating layer on the hard mask layer;
• removing the first insulating layer of the first area to leave a first insulating layer pattern on the second area;
• removing the hard mask layer of the first area;
• forming a second insulating layer on the conductive layer and the first insulating layer pattern to increase a height of an insulating layer on the second area;
• and
• removing the second insulating layer and the first insulating layer pattern until the stacked structure is exposed, thereby planarizing the first area and the second area;
• wherein
• the step of leaving the first insulating layer pattern on the second area comprises the sub-steps of:
• forming an etch-protecting layer on the first insulating layer;
• removing the etch-protecting layer of the first area via a photolithography process to form an etch-protecting layer pattern on the second area;
• removing the first insulating layer of the first area using the etch-protecting layer pattern as an etching mask;
• and
• removing the etch-protecting layer pattern.

A method of manufacturing a non-volatile flash memory device in which a flash memory cell is formed on a cell area of a semiconductor substrate and a logic device is formed on a peripheral circuit area, the method comprising the steps of:

• forming a floating gate structure on the cell area of the semiconductor substrate;
• forming a conductive layer on the floating gate structure and the semiconductor substrate;
• forming a hard mask layer on the conductive layer;
• forming a first insulating layer on the hard mask layer;
• removing the first insulating layer of the cell area to leave a first insulating layer pattern on the peripheral circuit area;
• removing the hard mask layer of the cell area;
• forming a second insulating layer on the conductive layer and the first insulating layer pattern to increase a height of the insulating layer on the peripheral circuit area;
• planarizing the cell area and the peripheral circuit area by removing the second insulating layer and the first insulating layer pattern until the floating gate structure is exposed;
• and
• patterning the conductive layer to form wordlines on both sidewalls of the floating gate structure and simultaneously to form a gate of the logic device on the peripheral circuit area;
• wherein
• the step of simultaneously forming the wordline and the gate comprises the substeps of:
• performing an oxidation process to form an oxide layer on the surface of the floating gate structure;
• removing the first insulating layer pattern and the second insulating layer;
• patterning the hard mask layer residue of the peripheral circuit area via a photolithography process to form a hard mask layer pattern;
• and
• etching the conductive layer using the oxide layer of the cell area and the hard mask layer pattern of the peripheral circuit area.