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US 6,649,453 B1Granted
Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation
AssigneeMicron Technology, Inc.
InventorsChun Chen, Andrei Mihnea, Kirk Prall
Life of this patent
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Abstract
Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.
Claims52
A method of setting a logic state of a memory cell in an array of memory cells, comprising:
- applying a first potential to a word line associated with the memory cell, wherein the first potential has a first polarity;
- applying a second potential to a first source/drain region and a second source/drain region of the memory cell, wherein the second potential has a second polarity;
- applying the second potential to a first well containing the first and second source/drain regions;
- and
- applying a third potential to a second well, wherein the second well is underlying the first well and is coupled to the first well through a PN junction.
2 more elements
A method of setting a logic state of a memory cell in an array of memory cells, comprising:
- applying a first potential to a word line associated with the memory cell, wherein the first potential has a first polarity;
- applying a second potential to a first source/drain region and a second source/drain region of the memory cell, wherein the second potential has a second polarity;
- applying the second potential to a first well containing the first and second source/drain regions;
- and
- applying a third potential to a second well underlying the first well, wherein the second well is coupled to the first well through a PN junction and wherein the third potential has the second polarity.
2 more elements
A method of setting a logic state of an array of memory cells arranged in rows and columns, the method comprising:
- applying a first potential to each word line of the array, wherein the first potential has a first polarity;
- applying a second potential to a first source/drain region and a second source/drain of each memory cell of the array, wherein the second potential has a second polarity, wherein each memory cell of a column of memory cells shares first and second source/drain regions and wherein each column of memory cells is formed in an isolated first well having a first conductivity type;
- applying the second potential to the first well of each column of memory cells;
- and
- applying a third potential to a second well, wherein the second well is underlying each first well and has a second conductivity type different than the first conductivity type.
2 more elements
A method of setting a logic state of an array of memory cells arranged in rows and columns, the method comprising:
- applying a first potential to each word line of the array, wherein the first potential has a first polarity;
- applying a second potential to a first source/drain region and a second source/drain of each memory cell of the array, wherein the second potential has a second polarity, wherein each memory cell of a column of memory cells shares first and second source/drain regions and wherein each column of memory cells is formed in an isolated first well having a first conductivity type;
- applying the second potential to the first well of each column of memory cells;
- and
- applying a third potential to a second well, wherein the second well is underlying each first well, wherein the second well has a second conductivity type different than the first conductivity type and wherein the third potential has the second polarity.
2 more elements
A method of forming an array of non-volatile memory cells, comprising:
- forming at least two isolation trenches in a substrate;
- forming a first well between each pair of isolation trenches, wherein each first well has a first conductivity type;
- forming a first source/drain region and a second source/drain region in each first well, wherein each first source/drain region is laterally separated from its associated second source/drain region to define an intermediate channel region and wherein each source/drain region has a second conductivity type different than the first conductivity type;
- forming a second well underlying and in contact with the isolation trenches, wherein the second well has the second conductivity type;
- forming a tunnel dielectric overlying at least the channel region;
- forming a floating gate overlying the tunnel dielectric;
- forming a control gate overlying the floating gate;
- and
- forming an interlayer dielectric between the floating gate and the control gate.
6 more elements
A method of forming an array of non-volatile memory cells, comprising:
- forming at least two isolation trenches in a substrate, wherein each isolation trench contains a dielectric material;
- conductively doping an exposed surface of the substrate to a first conductivity type between the isolation trenches, thereby forming first wells between each pair of isolation trenches;
- conductively doping a first portion and a second portion of a surface of each of the first wells to a second conductivity type opposite the first conductivity type, wherein each first portion of the first wells is laterally separated from its associated second portion;
- conductively doping a portion of the substrate underlying and in contact with the isolation trenches to the second conductivity type;
- forming a first dielectric layer overlying a surface of each first well;
- forming a first conductive layer overlying the first dielectric layer, wherein the first conductive layer is capable of holding a charge;
- forming a second dielectric layer overlying the first conductive layer;
- and
- forming a second conductive layer overlying the second dielectric layer.
6 more elements
A method of setting a logic state of a memory cell in an array of memory cells, comprising:
- applying a first potential to a word line associated with the memory cell, wherein the first potential has a first polarity;
- applying a second potential to a first source/drain region and a second source/drain region of the memory cell, wherein the second potential has the first polarity;
- applying the second potential to a first well containing the first and second source/drain regions;
- and
- applying a third potential to a second well, wherein the second well is underlying the first well and is coupled to the first well through a PN junction and wherein the third potential has the first polarity.
2 more elements
A method of setting a logic state of a memory cell in an array of memory cells, comprising:
- applying a first potential to a word line associated with the memory cell;
- applying a second potential to a first source/drain region and a second source/drain region of the memory cell;
- applying the second potential to a first well containing the first and second source/drain regions;
- and
- applying the second potential to a second well underlying the first well, wherein the second well is coupled to the first well through a PN junction;
- wherein the second potential is greater than the first potential.
3 more elements
A method of setting a logic state of an array of memory cells arranged in rows and columns, the method comprising:
- applying a first potential to each word line of the array;
- applying a second potential to a first source/drain region and a second source/drain of each memory cell of the array, wherein each memory cell of a column of memory cells shares first and second source/drain regions and wherein each column of memory cells is formed in an isolated first well having a first conductivity type;
- applying the second potential to the first well of each column of memory cells;
- and
- applying the second potential to a second well, wherein the second well is underlying each first well and has a second conductivity type different than the first conductivity type.
2 more elements
A method of setting a logic state of an array of memory cells arranged in rows and columns, the method comprising:
- applying a first potential to each word line of the array;
- applying a second potential to a first source/drain region and a second source/drain of each memory cell of the array, wherein each memory cell of a column of memory cells shares first and second source/drain regions and wherein each column of memory cells is formed in an isolated first well having a first conductivity type;
- applying the second potential to the first well of each column of memory cells;
- and
- applying the second potential to a second well, wherein the second well is underlying each first well and wherein the second well has a second conductivity type different than the first conductivity type.
2 more elements
Dependencies are inferred from the claim text.