Internally triggered electrostatic device clamp with stand-off voltage

An ESD protection device for protecting a circuit form ESD events between a first supply pad and a second supply pad to which the circuit is connected, wherein the circuit is designed with a stand-off voltage, the ESD protection device comprising:

• an ESD protection NMOS transistor having a drain coupled to the first supply pad and as source and a bulk region coupled to the second supply pad, said ESD protection NMOS transistor having a source-to-drain breakdown potential;
• a trigger NMOS transistor having a drain coupled to the first supply pad, said trigger NMOS transistor having and a source-to-drain breakdown potential higher than the stand-off voltage and less that said source-to-drain breakdown potential of said ESD protection NMOS transistor;
• and
• a resistor having a low-potential node coupled to the second supply pad and a high potential node coupled to a gate of said ESD protection NMOS transistor and to a gate, source, and bulk region of said trigger NMOS transistor, wherein said trigger NMOS transistor has an effective gate channel length less than an effective gate channel length of said ESD protection NMOS transistor.

A process for fabricating an ESD protection circuit formed of a compound transistor structure including an ESD protection transistor and a trigger transistor, the process comprising the steps of:

• forming an isolation layer of semiconductor material of a first conductivity on a semiconductor substrate;
• forming a first well of semiconductor material of second conductivity type in said semiconductor substrate;
• forming a second well of semiconductor material of second conductivity type in said isolation layer and spaced from said first well by said isolation layer;
• forming source and drain regions of semiconductor material of first conductivity type in said first well and said second well, wherein source and drain regions of said first well are spaced farther apart than said source and drain regions of said second well;
• and
• forming a first region of semiconductor material of second conductivity type in high enough concentration to form a connection to said first well, and a second region of semiconductor material of second conductivity type in high enough concentration to form a connection to said second well;
• forming gate for the transistor in said first and in said second wells
• connecting the source, well and gate of the transistor in the second well to the gate of the transistor in the first well,
• forming a resistance located outside of the fit well, and
• connecting the resistance from the gates of both transistors to a second supply pad and the drains of both transistors to a first supply pad, wherein the breakdown of the transistor in the second well is less than the breakdown of the transistor in the first well, where the snap-back voltage of the transistor in the second well is less that the snap back voltage of the transistor in the first well.

An ESD protection circuit formed of a compound transistor structure including an ESD protection transistor and a trigger transistor, the ESD protection circuit comprising:

• an isolation layer of semiconductor material of a first conductivity on a semiconductor substrate;
• a first well of semiconductor material of second conductivity type in said semiconductor substrate;
• a second well of semiconductor material in said isolation layer and spaced from said first well;
• source and drain regions of semiconductor material of first conductivity type in said first well and said second well, wherein source and drain regions of said first well are spaced farther apart than said source and drain regions of said second well;
• a first region of semiconductor material of second conductivity type in high enough concentration to form a connection to said first well, and a second region of semiconductor material of second conductivity type in high enough concentration to form a connection to said second well;
• a gate for the transistor in said first and in said second wells
• the source, well and gate of the transistor in the second well to the gate of the transistor in the first well,
• a resistance located outside of the first well,
• wherein the resistance connects from the gates of both transistors to a second supply pad and the drains of both transistors are connected to a first supply pad, wherein the breakdown of the transistor in the second well is less than the breakdown of the transistor in the first well, wherein the snapback voltage of the transistor in the second well is less that the snap back voltage of the transistor in the first well.