Semiconductor device, image display device, and method and apparatus for manufacture thereof
AssigneeHitachi, Ltd.
InventorsHajime Akimoto, Kozo Katayama
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Abstract
A switch device includes a source, a drain, and a gate electrode which are conductive, one or more semiconductor island layer(s) formed between the source and drain, an insulating film between the source and island layer, an insulating film between the drain and island layer, an insulating layer between island layers if a plurality of island layers are provided, and a gate capacitor formed by the gate electrode, at least one island layer, and a gate insulating film provided between the gate electrode and the island layer. The electric field applied to the gate capacitor is set to be substantially parallel with a channel current flowing via the island between the source and the drain.
Claims13
A semiconductor device comprising:
- a first conductive layer which functions as a source or drain;
- a semiconductor island layer formed over said first conductive layer, wherein a first insulating film is formed between said first conductive layer and said semiconductor island layer;
- a second conductive layer which functions as a source or drain formed over said semiconductor island layer, wherein a second insulating film is formed between said second conductive layer and said semiconductor island layer;
- and
- a gate electrode which is a conductive layer formed over said semiconductor island layer on a gate insulating film formed on said second insulating film,
- wherein in a first mode in which a first potential is applied to said gate electrode, a potential corresponding to said first potential is applied to said semiconductor island layer via parasitic capacitance formed by said gate electrode and said semiconductor island layer to thereby increase said semiconductor island layer potential, and a current is passed between said first and second conductive layers through said semiconductor island layer, said first insulating film and said second insulating film along a direction of an electric field applied between said gate electrode and said semiconductor island area, and
- in a second mode in which a second potential is applied to said gate electrode, a potential corresponding to said second potential is applied to said semiconductor island layer via a parasitic capacitance formed by said gate electrode and said semiconductor island layer to thereby decrease said semiconductor island layer potential, and a current is substantially inhibited from passing between said first and second conductive layers through said semiconductor island layer, said first insulating film and said second insulating film.
An image display device comprising pixel electrodes formed on a flat substrate and arranged in a matrix for forming a liquid-crystal capacitor with a common electrode formed to which a predetermined voltage is applied, a pixel switch provided for each of said pixel electrodes arranged in the matrix to write a display signal to said pixel electrode, write switch control means for controlling said pixel switch, a signal line connected to said pixel switch and provided for each column, and display signal input means for writing a display signal onto said signal line,
- wherein said pixel switch comprises:
- a first conductive layer which functions as a source or drain and is formed on a surface of said flat substrate and connected to said signal line;
- a semiconductor island layer formed over said first conductive layer, wherein a first insulating film is formed between said first conductive layer and said semiconductor island layer;
- a second conductive layer which functions as a source or drain formed over said semiconductor island layer and connected to said pixel electrode, wherein a second insulating film is formed between said second conductive layer and said semiconductor island layer;
- and
- a gate electrode which is a conductive layer formed over said semiconductor island layer on a gate insulating film formed on said second insulating film, and is connected to said write switch control means,
- wherein in a first mode in which a first potential is applied to said gate electrode by said write switch control means, a potential corresponding to said first potential is applied to said semiconductor island layer via parasitic capacitance formed by said gate electrode and said semiconductor island layer to thereby increase said semiconductor island layer potential, and a current is passed between said first and second conductive layers through said semiconductor island layer, said first insulating film and said second insulating film along a direction of an electric field applied between said gate electrode and said semiconductor island layer, and
- in a second mode in which a second potential is applied to said gate electrode by said write switch control means, a potential corresponding to said second potential is applied to said semiconductor island layer via the parasitic capacitance formed by said gate electrode and said semiconductor island layer to thereby decrease said semiconductor island layer potential, and a current is substantially inhibited from passing between said first and second conductive layers through said semiconductor island layer, said first insulating film and said second insulating film.
A method of manufacturing a switch device comprising:
- a first step of forming a first layer of polycrystalline silicon on a substrate, said first polycrystalline layer being conductive and doped with an impurity;
- a second step of forming a first thin insulating film on said first polycrystalline silicon layer;
- a third step of forming an amorphous silicon layer on said first thin insulating film and then irradiating said amorphous silicon layer with a laser beam to thereby convert said amorphous silicon layer into a second polycrystalline silicon layer;
- a fourth step of forming a second thin insulating film on said second polycrystalline silicon layer;
- a fifth step of forming a third polycrystalline silicon layer on said second thin insulating film, said third polycrystalline silicon layer being conductive and doped with an impurity;
- a sixth step of patterning said first polycrystalline silicon layer, said first thin insulating film, said second polycrystalline silicon layer, said second insulating film and said third polycrystalline silicon layer by dry etching using a single mask;
- a seventh step of removing part of said third polycrystalline silicon layer to expose at least a portion of said second thin insulating film;
- an eighth step of forming a gate insulating film on said exposed portion of said second thin insulating film;
- and
- a ninth step of forming a gate electrode on said gate insulating film.
Dependencies are inferred from the claim text.