Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng Chung Lin, Lain Jong Li
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng Chung Lin, Lain Jong Li
Estimating the term…
A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.
A method of forming a trench and via hole, comprising:
A method of forming a trench and via hole, comprising:
Dependencies are inferred from the claim text.